Multiplex communications – Wide area network – Packet switching
Patent
1993-08-31
1995-03-07
Marcelo, Melvin
Multiplex communications
Wide area network
Packet switching
370 8513, 370 941, H04J 326, H04L 1246, H04L 1256
Patent
active
053964934
ABSTRACT:
A local area network (LAN) bridge apparatus capable of carrying out the address learning and the packet filtering at a high speed, without requiring the program execution on the micro-processor for these purposes. The apparatus provides, besides the usual micro-processor and LAN controller, a dedicated mechanism including: a filtering address table (FAT) memory for registering FAT data containing a filtering address (FA); a FAT memory address generator for generating FAT memory addresses for specifying the FAT data in the FAT memory by compressing a sender address (SA) and a destination address (DA) of each packet transmitted from the LAN; an address learning circuit for obtaining the SA of each packet and registering the FAT data with the obtained SA as the FA in the FAT memory specified by the FAT memory address generated by the FAT memory address generator from the SA of each packet; a DA obtaining circuit for obtaining a DA from each packet; and a judging circuit for judging each packet as a packet to be discarded when the FA of the FAT data registered in the FAT memory specified by the FAT memory address generated by the FAT memory address generator from the DA of each packet coincides with the DA obtained by the DA obtaining circuit from each packet.
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patent: 5095480 (1992-03-01), Fenner
patent: 5136580 (1992-08-01), Videlock et al.
patent: 5151897 (1992-09-01), Suzuki
patent: 5224096 (1993-06-01), Onishi et al.
Kabushiki Kaisha Toshiba
Marcelo Melvin
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