Loading data with error detection in a power on sequence of...

Details Loading data with error detection in a power on sequence of... Loading data with error detection in a power on sequence of...

2006-10-05

2008-05-27

Pham, Ly Duy (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S189050, C365S189070, C365S190000

Reexamination Certificate

active

07379341

ABSTRACT:
A method of performing a power on sequence for a flash memory includes applying device voltage to the flash memory and loading nonvolatile memory data and nonvolatile memory complementary data to a read data register and a read complementary data register, respectively. The nonvolatile memory data and the nonvolatile memory complementary data are compared with the read data register and the read complementary data register during the power on sequence, e.g., after initial power up or power on reset (POR). When the comparison determines a mismatch, the loading of the nonvolatile memory data and the nonvolatile memory complementary data to the read data register and the read complementary data register, respectively, is repeated.

REFERENCES:
patent: 5784317 (1998-07-01), Ha
patent: 6654272 (2003-11-01), Santin et al.
patent: 6845029 (2005-01-01), Santin et al.
patent: 2007/0075869 (2007-04-01), Vazach et al.

Affiliated with

Also associated with

Rating

Loading data with error detection in a power on sequence of... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Loading data with error detection in a power on sequence of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Loading data with error detection in a power on sequence of... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3985998