Load/store with write-intent for write-back caches

Details Load/store with write-intent for write-back caches Load/store with write-intent for write-back caches

1988-09-16

1991-08-27

Shaw, Gareth D.

Boots, shoes, and leggings

3642281, 3642283, 3642434, 36424341, 36424344, G06F 1300

Patent

active

050438867

ABSTRACT:
A method for reading data blocks from main memory by central processing units in a multiprocessor system containing write-back caches. Load or gather instructions contain a write-intent flag. The status of the write-intent flag is determined. It is also determined whether a data block requested in the instruction by one of the processors is located in a corresponding cache, and if so, the requested data block is returned to the processor. If the data block is not in the cache and the write-intent flag indicates that the block will not be modified, the data block is read from main memory without obtaining a write privilege. The requested data block is subsequently returned from the cache to the processor. If the data block is not in the cache and the write-intent flag indicates the data block will be modified by the processor, then the data block is read from main memory while obtaining the write privilege. Subsequently, the requested data block is returned from the cache to the processor.

REFERENCES:
patent: 4394731 (1983-07-01), Flusche et al.
patent: 4442487 (1984-04-01), Fletcher et al.
patent: 4445174 (1984-04-01), Fletcher
patent: 4484267 (1984-11-01), Fletcher
patent: 4503497 (1985-03-01), Krygowski et al.
patent: 4691282 (1987-09-01), Kinoshita
patent: 4885680 (1989-12-01), Anthony et al.
Dubois and Briggs, "Effects of Cache Coherency in Multiprocessors", IEEE Transactions on Computers, vol. C-31, No. 11, Nov. 1982.

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