Drying and gas or vapor contact with solids – Process – With sealing of treating chamber
Reexamination Certificate
2000-10-27
2002-11-05
Wilson, Pamela (Department: 3749)
Drying and gas or vapor contact with solids
Process
With sealing of treating chamber
C034S487000, C034S242000, C414S217000, C414S937000, C414S940000
Reexamination Certificate
active
06473996
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a Front Opening Unified Pod (FOUP), which is a next-generation wafer carrier for holding, transporting, and storing a substrate such as a semiconductor wafer. The present invention further relates to a load port for opening and closing the pod, to a load port system including the FOUP, and to a method of treating or producing a substrate using the load port system. More particularly, the present invention is intended to improve the reliability of opening/closing action of a door of a FOUP and prevent entry of particles (extraneous particles) into a substrate treatment unit with sufficient reliability.
2. Background Art
In contrast with open cassettes which have conventionally been used (e.g., open cassettes which are incompatible with 8-inch wafers and typified by SEMI Standard E1.9), a side-door integral-type wafer carrier holds wafers in an enclosed space, to thereby protect wafers from dust particles in the atmosphere or from chemical contamination.
FIG. 9
is a perspective view for describing a FOUP system which is a side-door integral-type wafer carrier and has conventionally been used for manufacturing semiconductor devices. As shown in
FIG. 9
, P
30
denotes a FOUP system; P
1
denotes a FOUP shell (e.g., a pod main unit); P
2
denotes a FOUP door; P
5
denotes a latch key hole; P
8
denotes a sealing substance (e.g., a packing); P
9
denotes a door clamping mechanism (e.g., a stopper mechanism); and P
10
denotes a retainer.
The FOUP system P
30
shown in
FIG. 9
belongs to Front Opening Unified Pod systems, which are next-generation wafer carriers for holding, transporting, and storing substrates for use as photo-reticles, substrates for display panels such as substrates for liquid-crystal display panels or plasma displays, hard disk substrates, and substrates such as wafers for use in fabricating electronic devices such as semiconductor devices. The FOUP system P
30
is one described in, for example, a catalog describing F300 Wafer Carriers manufactured by Entegris. Information about detailed dimensions of the FOUP system are described in SEMI Standards E57, E1.9, E47.1. Such a side-door integral-type wafer carrier is hereinafter generically called a “FOUP system.”
In contrast with open cassettes which have conventionally been used (e.g., open cassettes which are incompatible with 8-inch wafers and typified by SEMI Standard E1.9), the conventional FOUP system holds wafers in an enclosed space, to thereby protect the wafers from dust particles in the atmosphere or from chemical contamination. In order to maintain air-tightness, the sealing substance P
8
(packing) is provided along the edge of the FOUP door P
2
. The FOUP door P
2
has a wafer press mechanism called the retainer P
10
, beams called a wafer teeth section (not shown) for seating wafers, and a mechanical opening/closing mechanism such as the door clamp mechanism P
9
.
In order to open and close such a FOUP system P
30
in a semiconductor manufacturing system (e.g., a substrate treatment unit), there is a necessity for use of a load port having a FIMS (Front-Opening Interface Mechanical Standard) surface specified by a SEMI standard.
The load port has a kinematic pin for sustaining the FOUP system P
30
in a fixed position, a FIMS door which engages with the FOUP door P
2
and is taken into an mini-environment defined in the FOUP system
30
along with the FOUP door P
2
after the FOUP door P
2
has been opened (i.e., after a latch key has been rotated), and a housing surface for isolating the mini-environment from the outside. An area in the housing surface of the load port which is to engage with a FOUP sealing surface of the FOUP system P
30
is called an FIMS sealing surface.
A wafer holding section of such a conventional wafer carrier (or FOUP system) P
30
is primarily made up of the FOUP shell section P
1
and the FOUP door P
2
which is an open/close door. In order to secure the FOUP door P
2
to the FOUP shell section P
1
, there is a necessity for the door clamping mechanism P
9
(e.g., a stopper mechanism). For this reason, the wafer holding section has a complicated structure, and a hole must be provided in the FOUP door P
2
. Further, a hole to be clamped for securing a door must be provided even in the FOUP shell section P
1
. Further, the FOUP shell section P
1
must have a thick section and a sealing section.
At worksites, a plurality of types of load ports and a plurality of types of wafer carrier jigs (FOUP systems) P
30
must be used in combination. Accordingly, higher dimensional accuracy is required. Even minute deformation greatly affects the reliability of opening and closing action of a FOUP door.
The background art encounters the following problems. A first drawback of the background art is that, when the sealing substance P
8
(i.e., a packing) provided on the sealing surface of the FOUP shell section P
1
is brought into contact with the FIMS sealing surface, sustaining the FOUP system P
30
in such a position and opening/closing the FOUP system P
30
with high reliability are difficult.
A second problem is that, when the sealing surface of the FOUP shell section P
1
remains in contact with the FIMS sealing surface, flow of clean air from the mini-environment defined in the treatment unit (i.e., the inside of the FOUP system P
30
) to the outside thereof is limited. This is not preferable in terms of contamination. Particularly, prevention of entry of particles (extraneous particles) into the treatment unit (the inside of the FOUP system P
30
) is insufficiently reliable.
SUMMARY OF THE INVENTION
The present invention has been conceived to solve these drawbacks of the background art and is aimed at providing a load port structure and a FOUP structure which enable high-yield production of integrated circuits by means of improving the reliability of opening/closing action of a FOUP door and preventing entry of particles into the treatment unit with sufficient reliability. Further, the present invention has been conceived to provide a production method using the improved load port structure and the FOUP structure.
According to the aspects of the present invention, a load port system for use with a substrate treatment unit is improved, in which a wafer carrier having wafers stored therein is placed on a load port of the substrate treatment unit, a load port door opposes a door of the wafer carrier, and a sealing surface provided around the load port door opposes a sealing surface provided around a door opening section of the wafer carrier.
In the load port system, a plurality of protuberances, which are to be brought into contact with the sealing surface provided around the door opening section of the wafer carrier, are provided on the sealing surface formed around the load port door of the substrate treatment unit.
Alternatively, a plurality of protuberances, which are to be brought into contact with the sealing surface provided around the load port door of the substrate treatment unit, are provided on the sealing surface formed around the door opening section of the wafer carrier.
Thereby, a predetermined clearance is maintained between the sealing surface provided around the load port door and the sealing surface provided around the door opening section of the wafer carrier.
Other features and advantages of the invention will be apparent from the following description taken in connection with the accompanying drawings.
REFERENCES:
patent: 5609459 (1997-03-01), Muka et al.
patent: 5613821 (1997-03-01), Muka et al.
patent: 5664925 (1997-09-01), Muka et al.
patent: 6082949 (2000-07-01), Rosenquist
patent: 6120229 (2000-09-01), Hofmeister
patent: 5-109865 (1993-04-01), None
Patent Abstract of Japan, “Production of Magnetic Head”, JP 10-124812, May 15, 1998, Japanese Patent Office.
Foley & Lardner
Semiconductor Leading Edge Technologies Inc.
Wilson Pamela
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