Load for non-volatile memory drain bias

Details Load for non-volatile memory drain bias Load for non-volatile memory drain bias

2000-12-29

2003-05-27

Elms, Richard (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185210, C365S185180

Reexamination Certificate

active

06570789

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to computer memory in general, and more specifically to providing a load for non-volatile memory drain bias.
BACKGROUND OF THE INVENTION
Non-volatile memory that can retain information when a power supply is switched off, such as flash memory, is being used increasingly in electronic devices for personal and commercial use, including cellular telephones, digital cameras, embedded devices, and personal data assistants. Flash memory is well suited for such uses because it is electrically erasable and can be reprogrammed within normal circuit parameters, without requiring special programming devices operating at higher than normal voltage levels.
Technology has made it possible to produce flash memory that is increasingly dense, resulting in greater and greater amounts of memory being available to electronic products. However, increasing the density of memory results in increased power consumption. Further, in order to reduce the power consumption of these products, there has also been an attempt to operate flash memory at lower voltages and to utilize low power circuits, which presents additional challenges to keep up with performance demand and cost restraints.
Flash memory is composed of flash cells that require a certain drain voltage for proper operation. The function of a drain bias circuit is to provide the necessary drain voltage to a flash cell. The load in a drain bias converts the current differential between the data flash cell and the reference cell to a voltage differential at the data array sense input node (SIN node) or reference array input node (RIN node) for the sense amplifier to sense. In 1:1 sensing operation, for each sense amplifier there is one drain bias circuit provided for the array side and one provided for the reference side. When there is no sensing operation, the drain bias circuit may be turned off and thus does not sink any current. Before sensing operations commence, it is necessary to turn the drain bias on, and thereby cause current flow. When turned on, the drain bias circuit begins charging the bitline or column, and in addition begins to develop the voltage margin that the sensing amplifier will be sensing. It is important to charge the bitline quickly in order to achieve sufficiently fast sensing speed.
A typical drain biasing circuit may include a biasing feedback inverter. As the data size (the number of bits being read at one time) and density of non-volatile memory are increased, a drain bias circuit with a biasing feedback inverter may pose difficulties because the biasing feedback inverter sinks a relatively high amount of current. The current for each such circuit may be in the range of 100 to 200 microamps. As more flash memory cells are read simultaneously, the resulting power consumption also rises. In addition, the physical area occupied by such a drain bias circuit needs to be relatively large for sufficient speed of operation.
The development of non-volatile memory has moved towards reading more memory cells simultaneously, thus requiring additional sensing amplifiers and drain bias circuits. As more drain bias circuits are required for sensing more memory cells, the physical space in a semiconductor device that is dedicated to this function also increases. For example, in ×64 sensing, in which the values of 64 memory cells are read at a time, there are 128 drain bias circuits, resulting in significant current drain and physical space requirements. As the physical area for drain bias circuits increases, the parasitic capacitance created generally will also increase, and this capacitance creates power losses in the memory device.
In addition to non-volatile memory moving towards larger scale devices, the device supply voltages levels have also been reduced to save power in operation and extend the life of power sources. As non-volatile memory moves to these lower supply voltages, it becomes more difficult to bring voltages up to necessary operating levels quickly so as not to sacrifice speed of memory operation.


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