Load equalization in digital delay interpolators

Details Load equalization in digital delay interpolators Load equalization in digital delay interpolators

2001-01-05

2002-04-23

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S278000, C327S294000, C327S400000

Reexamination Certificate

active

06377102

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates to tristatable circuit elements. More particularly, the present invention relates to digital delay interpolators, specifically, to an apparatus for generating uniform delays in digital delay interpolators.
BACKGROUND OF THE INVENTION
Weighted interpolation of digital delay taps is a known technique for subdividing the delay into finer delays for better resolution, for example in delay locked loops.
FIG. 1
shows a typical prior art delay chain
10
, which may, for example, be part of a ring oscillator. The delay chain
10
is made of four delay elements
12
,
14
,
16
,
18
connected in series, as shown. An input signal IN is applied to the input of the first delay element
12
, and it is passed down the chain
10
. Each element in the chain
10
gives the input signal a delay of T. Thus, the signal at the output of delay element
12
has a delay of T with respect to signal IN, the signal at the output of delay element
14
has a delay of 2T with respect to signal IN, the signal at the output of delay element
16
has a delay of 3T with respect to signal IN, and the signal at the output of delay element
18
has a delay of 4T with respect to signal IN.
FIG. 2
shows a typical prior art digital delay interpolator
20
. The interpolator
20
is made of two groups of delay elements, in this case each being an inverter. The first group, on the left of the figure, is comprised of four delay elements i
1
L, i
2
L, i
3
L and i
4
L, of equal strength, each having its input connected to receive a signal L on line
22
, while the second group is comprised of four delay elements i
1
R, i
2
R, i
3
R and i
4
R, of equal strength, each having its input connected to receive a signal R on line
24
. Each delay element receives a respective differential pair of enable signals Delay elements i
1
L and i
1
R receive enable signals EN
1
and {overscore (EN
1
)}, delay elements i
2
L and i
2
R receive enable signals EN
2
and {overscore (EN
2
)}, delay elements i
3
L and i
3
R receive enable signals EN
3
and {overscore (EN
3
)}, while delay elements i
4
L and i
4
R receive enable signals EN
4
and {overscore (EN
4
)}. The signals L and R may be, for example, the outputs of two adjacent delay elements of the delay chain
10
of
FIG. 1
, such as delay element
12
and delay element
14
for example. In this discussion it is assumed that signal R is delayed more than signal L.
Delay interpolator
20
functions to cause the timing of its output signal OUT to be controlled incrementally more or less by the timing of signal L or signal R, depending on which of its delay elements are selected for enablement, i.e., their associated enable signal is ON. Thus, the delay through interpolator
20
may be subdivided into, for example four T/4 delays and thereby provide a finer gradation of delay when used with, for example, the delay chain
10
of FIG.
1
. The delay elements in the interpolator
20
are tristatable inverters and at any given time four out of the eight inverters are ON, i.e., enabled. Minimum delay is achieved when all four inverters receiving the L signal (i
1
L, i
2
L, i
3
L and i
4
L) are ON. The next greater delay is achieved when three inverters receiving L and one inverter receiving R are ON. The next greater delay is achieved when two inverters receiving L and two inverters receiving R are ON. The next greater delay is achieved when one inverter receiving L and three inverters receiving R are ON. Maximum delay is achieved when all four inverters receiving the R signal (i
1
R, i
2
R, i
3
R and i
4
R) are ON.
Now, assume that interpolation is to be between a delay of 2T and 3T by selecting the signal from
FIG. 1
delayed by 2T, i.e., the output of delay element
14
, to be signal L and by selecting the signal from
FIG. 1
delayed by 3T, i.e., the output of delay element
16
, to be signal R. Assume that the inherent delay due to any four of the tristatable inverters driving the output is t. When all of the L delay elements, i
1
L, i
2
L, i
3
L and i
4
L, are ON (the rest are OFF) the delay through interpolator
20
is equal to 2T+0+t. When delay elements i
1
R, i
2
L, i
3
L and i
4
L, are ON the delay through interpolator
20
is equal to 2T+T/4+t. When delay elements i
1
R, i
2
R, i
3
L and i
4
L, are ON the delay through interpolator
20
is equal to 2T+2T/4+t. Likewise, when delay elements i
1
R, i
2
R, i
3
R and i
4
R, are ON the delay through interpolator
20
is equal to 2T+4T/4+t, or, 3T+t.
However, the delays expressed above are theoretical delays. In reality, these delays are significantly shorter than expressed above, and these delays vary depending upon the delay selected. This is because of parasitic capacitances in the tristatable inverters, giving rise to capacitance at the interpolated output OUT, and because the capacitive load at output OUT is not the same in all cases.
The capacitance at the output of any given tristatable inverter in interpolator
20
depends on the voltage at its input, even when it is in the OFF state.
FIG. 3
is a circuit diagram of one of these inverters, each of which has the same construction. As can be seen, the capacitance at the output of the inverter is the sum of the gate to drain capacitances of the PMOS transistor
30
and NMOS transistor
32
, i.e., C
gdp
and C
gdn
, respectively, and of the back gate to drain capacitances of PMOS transistor
30
and NMOS transistor
32
, i.e., C
bdp
and C
bdn
, respectively. Normally, if the input signal IN is HIGH the values for C
gdn
and C
bdn
are also high, while if IN is low the values for C
gdp
and C
bdp
are high, resulting in a relatively high capacitive load at the output of this circuit in such cases. However, if IN is somewhere near mid-supply the capacitive contributions from both PMOS transistor
30
and NMOS transistor
32
are almost equal and the total capacitance is low. Consequently, the capacitive load at the output of this circuit is small in this case. An additional effect is that any rising or falling transition of the input signal IN is coupled to the output through C
gdp
and C
gdn
, and affects the output.
Because of these effects, the interpolated delays vary from the ideal magnitude expressed above. FIGS.
4
(A) and
4
(B) will now be referred to, to explain this further. These figures are signal diagrams in which the horizontal axis represents time and the vertical axis represents voltage. In both figures ten signals appearing at the output of the interpolator
20
of
FIG. 2
are superimposed, each such signal having successively greater delay, as shown by transitions
34
,
36
,
38
,
40
,
42
, etc. It is assumed that, initially, the signal L is the output of delay element
14
, while signal R is the output of delay element
16
, accounting for the first five transitions, and that after the fifth transition the signal L is the output of delay element
16
, while signal R is the output of delay element
18
, accounting for the next five transitions.
Consider transition
34
in
FIG. 4. A
transition delayed by tristate inverters i
1
L, i
2
L, i
3
L and i
4
L, has this delay. During this transition, signal R is HIGH, and therefore the capacitive load due to tristate inverters i
1
R, i
2
R, i
3
R and i
4
R, is maximum. The corresponding delay through interpolator
20
is, likewise, maximum.
However, consider transition
42
. A transition delayed by tristate inverters i
1
R, i
2
R, i
3
R and i
4
R, has this delay. During this transition, signal L is completing a transition, and hence the effective capacitive load offered by tristate inverters i
1
L, i
2
L, i
3
L and i
4
L, is much less than the load in the capacitive load in the previous case. The corresponding delay through interpolator
20
is, likewise, minimum. For intermediate transitions
36
,
38
and
40
, the same considerations apply, with decreasing load capacitance, and correspondingly decreasing delay, respectively. This creates a “dead zone” in the delay interpolation by compressing the delays as the t

Affiliated with

Also associated with

Rating

Load equalization in digital delay interpolators does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Load equalization in digital delay interpolators, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Load equalization in digital delay interpolators will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2888233