Load double test instruction

Details Load double test instruction Load double test instruction

1984-10-01

1987-07-07

Fleming, Michael R.

Excavating

364300, 364900, G06F 1100

Patent

active

046791949

ABSTRACT:
In a data processor having an instruction which requires the loading of the contents of two (2) successive locations in the address space during respective bus cycles, test circuitry is provided to selectively force the processor to twice load the contents of the same location upon execution of the instruction. Using this special load double test instruction, the processor is able to detect more precisely when the contents of the memory location changes in value as a result of the activity of other circuitry.

REFERENCES:
patent: 3921142 (1975-11-01), Bryant
patent: 4024386 (1977-05-01), Caudel
patent: 4128873 (1978-12-01), Lamiaux
patent: 4206503 (1980-06-01), Woods
patent: 4298958 (1981-11-01), Takaki et al.
patent: 4308581 (1981-12-01), Raglunathan
patent: 4315313 (1982-02-01), Armstrong
patent: 4604694 (1986-08-01), Hough

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