Load balanced scalable network gateway processor architecture

Details Load balanced scalable network gateway processor architecture Load balanced scalable network gateway processor architecture

2007-10-16

2007-10-16

Chan, Wing (Department: 2616)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S392000, C370S396000

Reexamination Certificate

active

09976229

ABSTRACT:
A network gateway processor architecture including a scalable array of compute processors that function to convert inbound data packets to outbound data packets, an ingress processor coupleable to a first network to receive the inbound data packets and coupled to provide the inbound data packets to the compute processors, and an egress processor coupleable to a second network and coupled to the compute processors to collect and forward the outbound data packets to the second network. The ingress processor distributes inbound data packets to the compute processors based on a least load value selected from current load values determined for the respective compute processors of the scalable array. The current load values represent estimated processing completion times for the respective compute processors of the scalable array of compute processors. Preferably, the current load values are dynamically derived with respect to the size of the inbound data packets and the performance of the respective compute processors.

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