Load and leave memory cell

Details Load and leave memory cell Load and leave memory cell

1997-02-26

1999-03-30

Nguyen, Tan T.

Static information storage and retrieval

Floating gate

Particular connection

365150, 36518523, G11C 1600

Patent

active

058897046

ABSTRACT:
A semiconductor EEPROM memory cell having a control circuit and an internal memory device for providing high speed electronic data storage (i.e. writing binary 1 and 0 functionality) in a relatively small physical area. In general, internal memory device has a floating gate, and a source, a drain and a gate coupled to the control circuit. In operation, the control circuit provides electrical signals to the source, drain and gate to control the writing of electrical data to and reading of electrical data from the internal memory device. When writing data to the memory device the control circuit provides electrical signals to the source, drain and gate to initiate electron tunneling between the floating gate and drain, wherein the electron tunneling ultimately produces a conductive or nonconductive state representing the data stored by the internal memory device. Similarly, when reading data from the internal memory device, the control circuit couples the drain, source and gate to a given electrical signal to detect the conductive or nonconductive state (i.e. the data) stored by the internal memory device.

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patent: 5557569 (1996-09-01), Smayling et al.
patent: 5615147 (1997-03-01), Chang et al.
patent: 5633518 (1997-05-01), Broze

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