Load address dependency mechanism system and method in a...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...

Reexamination Certificate

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Details

C712S217000, C712S219000, C711S125000, C711S140000

Reexamination Certificate

active

10992381

ABSTRACT:
The present invention provides for a method for a load address dependency mechanism in a high frequency, low power processor. A load instruction corresponding to a memory address is received. At least one unexecuted preceding instruction corresponding to the memory address is identified. The load instruction is stored in a miss queue. And the load instruction is tagged as a local miss.

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patent: 6079002 (2000-06-01), Thatcher et al.
patent: 6226713 (2001-05-01), Mehrotra
patent: 6247124 (2001-06-01), Joshi et al.
patent: 6732236 (2004-05-01), Favor
patent: 2002/0091914 (2002-07-01), Merchant et al.
A Large, fast instruction window for tolerating cache misses by Lebeck, A. R. et al. published 2002, ISBN: 0-7695-1605-x, (ICSA '02), pp. 59-70.

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