Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
Reexamination Certificate
2008-04-22
2008-04-22
Sough, Hyung S. (Department: 2188)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
C712S217000, C712S219000, C711S125000, C711S140000
Reexamination Certificate
active
07363468
ABSTRACT:
The present invention provides for a method for a load address dependency mechanism in a high frequency, low power processor. A load instruction corresponding to a memory address is received. At least one unexecuted preceding instruction corresponding to the memory address is identified. The load instruction is stored in a miss queue. And the load instruction is tagged as a local miss.
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A Large, fast instruction window for tolerating cache misses by Lebeck, A. R. et al. published 2002, ISBN: 0-7695-1605-x, (ICSA '02), pp. 59-70.
Barrick Brian David
Fensler Kimberly Marie
Hicks Dwain Alan
Osanai Takeki
Ray David Scott
Carr LLP
International Business Machines - Corporation
Patel Kaushik
Rifai D'Ann N.
Sough Hyung S.
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