Lithography method for direct alignment of integrated circuits m

Details Lithography method for direct alignment of integrated circuits m Lithography method for direct alignment of integrated circuits m

1994-05-04

1995-04-04

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

29 2501, H01L 2131, H01L 21312

Patent

active

054037549

ABSTRACT:
An alignment process (30) for use during the lithography process of producing multiple layer (24-26) integrated circuits. The location of each previous layer (24-26) in the integrated circuit is measured and evaluated with respect to each other and the wafer (14). The next layer is placed on the wafer (14) in a manner which optimizes its alignment relationship to each of the previous layers (24-26). Weighting factors are used to optimize alignment in multiple layer (24-26) integrated circuits.

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patent: 5005046 (1991-04-01), Hashimoto
Glen Zorpetti, "Rethinking X-ray Lithography," IEEE, Jun., 1992, pp. 32-36.
Alec Broers, "Choices for Tomorrow's Chips", New Scientist, Apr. 18, 1992, pp. 23-27.
Wm. C. Ward, "Volume Production of Unique Plastic Surface-Mount Modules for the IBM 80-ns 1-Mbit Dram Chip by Area Wire Bond Techniques," IEEE, 0569-5503/88/0000-0552, pp. 552-557 (1988).

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