Radiation imagery chemistry: process – composition – or product th – Radiation modifying product or process of making – Radiation mask
Reexamination Certificate
1999-08-17
2001-04-10
Rosasco, S. (Department: 1756)
Radiation imagery chemistry: process, composition, or product th
Radiation modifying product or process of making
Radiation mask
C430S296000
Reexamination Certificate
active
06214498
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a lithography mask and a fabricating method thereof, more particularly, to a mask or an aperture for lithography using electron or ion beams in a semiconductor device and a fabricating method thereof which improves thermal stability of a mask by forming a stencil mask of double structures comprised of an upper mask that absorbs and releases most of electron energy and a lower mask that defines patterns with electron/ion beams, thereby improving the reliance of fine patterns on an exposure process.
2. Discussion of Related Art
There are various kinds of lithography processes for fabricating a semiconductor device such as optical lithography, electron beam lithography, ion beam lithography, X-ray lithography and the like. They are sorted by the species of lights irradiated during each of the lithography processes. For all of the lithographies, the mask is one of the challenges. In optical lithography, generally, quartz or glass is transparent and a thin metal film is highly absorbing. In other lithographies, the radiation has more energy per particle such as photon, ion or electron and so the task of forming a spatially varying dose by means of a mask is more difficult.
In a lithography process, after a mask having predetermined patterns has been fabricated, an exposure step is accomplished by irradiating lights or beams selectively to the resist on a substrate through the mask. Thus, it is the major concern of the lithography that a precise mask pattern should be defined.
A stencil mask is used in electron beam lithography or ion beam lithography. The stencil mask is back ‘illuminated’ by a broad beam of ions or electrons, and its demagnified image is projected onto a resist covered substrate.
Unfortunately, as the energy of the projected particles is very large and the pattern images become more microscopic, distortion is generated on the mask pattern. The main sources of distortion are thought to be stress relief due to the cutting of holes and the thermal expansion due to mask heating by the incident electrons/ions. In this case, the generated heat is lost by radiation and by conduction, generally. Namely, heat is lost by radial conduction and by radiation from the mask's face.
A stencil mask of a thin film is fabricated by a process of fabricating a semiconductor device using a semiconductor substrate of silicon, etc., which is disclosed in U.S. Pat. No. 5,770,336.
FIG. 1A
to
FIG. 1F
show cross-sectional views of fabricating a lithography mask in a semiconductor device according to a related art.
Referring to
FIG. 1A
, surfaces of first and second silicon layers
10
and
12
of a silicon on insulator(hereinafter abbreviated SOI) wafer is planarized by chemical mechanical polishing(hereinafter abbreviated CMP). In this case, a silicon oxide layer
11
is inserted in the SOI wafer between the first and second silicon layers
10
and
12
. The silicon oxide layer
11
insulates the first and second silicon layers
10
and
12
from each other.
Referring to
FIG. 1B
, an insulating layer to form a hard mask is formed by depositing an oxide layer about 1.0 &mgr;m thick on an exposed surface of the second silicon layer
12
by chemical vapor deposition(hereinafter abbreviated CVD).
After the insulating layer of oxide has been coated with photoresist, a first photoresist pattern
14
is defined by exposure and development in use of electron beams to form a first stencil mask pattern on the second silicon layer
12
.
A portion of the oxide layer is removed by etching the oxide layer in use of the first photoresist pattern
14
as an etch mask. Thus, an oxide layer
13
beneath the first photoresist pattern
14
remains only.
Referring to
FIG. 1C
, a first stencil mask pattern
120
is formed by removing a portion of the second silicon layer which is not covered with the remaining oxide layer
13
and the first photoresist pattern
14
by means of dry etch.
Then, a surface of the remaining second silicon layer
120
, side faces of the insulating layer
110
of oxide and a partial surface of the first silicon layer
10
are exposed by removing the first photoresist pattern
14
and the remaining oxide layer
13
.
A nitride layer
15
is formed to the predetermined thickness on a whole surface of the wafer including the exposed second silicon layer
120
, the side faces of the insulating interlayer
110
of oxide and the first silicon layer
10
by CVD.
Referring to
FIG. 1D
, a bottom surface of the first silicon layer
10
is laid upward by turning upside down the wafer. After the nitride layer
15
on the surface of the first silicon layer
10
has been coated with photoresist, a second photoresist pattern
16
to define a second stencil pattern on the first silicon layer
10
is defined by carrying out exposure and development on the photoresist. In this case, the second photoresist pattern
16
is formed to correspond to the first stencil pattern
120
consisting of the remaining second silicon layer
120
. And, the size of the second photoresist pattern
16
is decided to give a second stencil pattern, which will be formed, a desired critical dimension.
Referring to
FIG. 1E
, an etch mask
150
on the first silicon layer
101
is formed by removing a portion of the nitride layer which is not covered with the second photoresist pattern on the first silicon layer. The, portion of the nitride layer within the apertures of the first stencil pattern
120
is exposed by etching the first silicon layer exposed by the etch mask
150
.
Thus, a second stencil pattern
101
consisting of the remaining first silicon layer
101
is formed. Yet, a stencil mask is not completed because a portion of the nitride layer
150
still remains at the boundary between the first and second stencil patterns
120
and
101
where the apertures are formed. Referring to
FIG. 1F
, the remaining nitride layer on a whole surface of the wafer is removed by wet etch. Thus, the whole surfaces of the first and second stencil patterns except the portions which are attached to the insulating interlayer
110
, as well as the side faces of the insulating interlayer
110
in the apertures, are exposed.
A conductive layer
17
is formed by depositing Pt, Ti or the like on the exposed surface of the wafer by sputtering or CVD. The conductive layer
17
discharges electrons from electron/ion beams.
Accordingly, a stencil mask comprised of the first and second stencil patterns
120
and
101
and the insulating interlayer
110
inserted between the patterns are fabricated.
Further, an electrically-conductive holder, as not shown in the drawing, is attached to the bottom edges of the first stencil pattern
120
.
FIG. 2
shows a cross-sectional view of a lithography mask in a semiconductor device according to a related art.
Referring to
FIG. 2
, a support
21
of a stencil mask is mounted on a holder
23
made of metal. There are a plurality of apertures forming a predetermined pattern
22
in a thin wafer, and the support
21
is located at the edge of the wafer.
A metal layer
24
of Pt, Ti or the like is formed on a whole surface of the stencil mask. A window at the lower part of the stencil mask helps electron/ion beams pass through the apertures easily.
A portion of the projected electron or ion beams E
1
successfully passes through the apertures to carry out exposure on a resist coated substrate, while the other portion of the beams E
2
blocked by the pattern
22
is discharged outside through the metal layer
24
and the holder
23
.
So, a portion of the electron beams E
1
passes through the apertures among the pattern
22
and the rest electron beams E
2
are blocked by the pattern
22
of silicon, wherein the window is formed by etching the underpart of the stencil mask. Thus, a resist pattern is defined by selective exposure onto the resist below the stencil mask. And, electrons blocked by the stencil mask are grounded through the metal layer
24
of the stencil mask as well as heat generated by irradiated electron
Fleshner & Kim LLP
Hyundai Electronics Industries Co,. Ltd.
Rosasco S.
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