X-ray or gamma ray systems or devices – Source – Electron tube
Reexamination Certificate
1995-06-07
2004-03-30
Church, Craig E. (Department: 2882)
X-ray or gamma ray systems or devices
Source
Electron tube
Reexamination Certificate
active
06714625
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to methods for fabricating integrated circuits on and in flexible membranes, and to structures fabricated using such methods.
2. Description of Related Art
Mechanically and thermally durable free standing dielectric and semiconductor membranes have been disclosed with thicknesses of less than 2 &mgr;m. (See commonly invented U.S. Pat. No. 4,924,589, and U.S. patent application Ser. No. 07/482,135, filed Feb. 16, 1990, now U.S. Pat. No. 5,103,557, both incorporated herein by reference). This disclosure combines the novel use of these technologies and other integrated circuit (IC) processing techniques to form ICs as membranes typically less than 8 &mgr;m thick. This approach to IC fabrication falls under the generic industry-established title known as Dielectric Isolation (DI), and is inclusive of subject areas such as Silicon-on-Insulator (SOI) and Silicon-on-Sapphire (SOS). ICs formed from dielectric and semiconductor membranes can reduce significantly the number and complexity of processing steps presently used to provide complete IC device isolation; dielectric isolation techniques that provide dielectric isolation on all surfaces of the individual circuit devices comprising the complete IC are not as yet widely used in volume IC fabrication. Integrated Circuits are defined as commonly understood today when referring to SSI, MSI, LSI, VLSI, ULSI, etc. levels of circuit complexity.
SUMMARY OF THE INVENTION
This invention is directed to a general method for the fabrication of integrated circuits and interconnect metallization structures from membranes of dielectric and semiconductor materials. The fabrication technology in accordance with this invention is referred to herein as Membrane Dielectric Isolation (MDI), and the circuits made from it as circuit membranes. The novel use of materials and processing techniques provides for the fabrication of high temperature, mechanically durable, large area free standing membranes (greater than 1 square cm in area) from low stress dielectric and/or semiconductor films. These membranes permit the application (continued use) of most of the established integrated processing methods for the fabrication of circuit devices and interconnect metallization.
In accordance with the invention, an integrated circuit is formed on a tensile low stress dielectric membrane comprised of one layer or a partial layer of semiconductor material in which are formed circuit devices and several layers of dielectric and interconnect metallization. Also, a structure in accordance with the invention is a tensile membrane of semiconductor material in which are formed circuit devices with multiple layers of tensile low stress dielectric and metallization interconnect on either side of the semiconductor membrane.
The membrane structure is a processing or manufacturing structure for enabling the manufacture of novel and more cost effective integrated circuits. This is in addition to an objective to manufacture an integrated circuit, or portion thereof, in a membrane or thin film form.
The general categories of circuit membranes that can be made by this invention are:
1. Large scale dielectric isolated integrated circuits formed on or from semiconductor or non-semiconductor substrates.
2. Multi-layer interconnect metallization circuits formed on or from semiconductor or non-semiconductor substrates.
The primary objectives of the MDI fabrication technology disclosed herein are the cost effective manufacture of high performance, high density integrated circuits and integrated circuit interconnect with the elimination or reduction of detrimental electrical effects on the operation of individual circuit devices (e.g. diodes, transistors, etc.) by completely isolating with a dielectric material each such circuit device from the common substrate upon which they are initially fabricated, and therefore, from each other, and to provide a more versatile and efficient physical form factor for the application of integrate circuits. Some of the benefits of the MDI IC fabrication process are the elimination or reduction of substrate current leakage, capacitive coupling and parasitic transistor effects between adjoining circuit devices. The MDI IC fabrication process benefits extend to several other categories of IC fabrication such as lower IC processing costs due to fewer IC isolation processing steps, greater IC transistor densities through the capability to use established IC processing techniques to fabricate interconnect metallization on both sides of a MDI IC circuit membrane, and greater IC performance through novel transistor structures.
The strength of the MDI processes is primarily drawn from two areas:
(1) The ability to make a large area flexible thin film free standing dielectric membrane, typically framed or suspended or constrained at its edges by a substrate frame or ring, or bonded frame or ring. This membrane is able to withstand a wide range of IC processing techniques and processing temperatures (of at least 400° C.) without noticeable deficiency in performance. The present dielectric materials that meet these requirements are silicon dioxide and silicon nitride films when prepared with specific low stress film deposition recipes for instance on equipment supplied by Novellus Systems, Inc. Dielectric free standing films created by CVD process methods such as silicon carbide, boron nitride, boron carbon nitride aluminum oxide, aluminum nitride, tantalum pentoxide, germanium nitride, calcium fluoride, and diamond have been produced, and can potentially be used as one of the dielectric materials in a MDI circuit membrane when deposited at an appropriate level of surface stress. Advances in the technology for making low stress dielectric films will likely produce additional free standing films that can be used as described herein.
(2) The ability to form a uniform thin film single crystal semiconductor substrate either as the primary substrate of semiconductor devices or as a carrier substrate upon which semiconductor devices could be grown epitaxially. Several methods toward this end are disclosed herein, and other techniques which are modifications thereof exist. Further, in certain applications polycrystalline semiconductor membranes such as polysilicon can be used in substitution for monocrystalline material.
It is the combination of the use of low stress free standing dielectric films with the appropriate processing qualities and membrane or thin film single crystalline (monocrystalline), polycrystalline or amorphous semiconductor substrate formation that provides much of the advantage of the MDI IC fabrication process. The following methods are encompassed within the present disclosure:
1. Methods for the fabrication of low stress free standing (thin film) dielectric membranes that encapsulate each semiconductor device that comprises an IC.
2. Methods for the formation of uniform thickness semiconductor membrane (thin film) substrates for use in combination with low stress dielectric materials.
3. Methods for the fabrication of semiconductor devices within and on a dielectric membrane that comprises a circuit membrane.
4. Methods for the formation of interconnect metallization structures within and on a dielectric membrane that comprises a circuit membrane.
The MDI circuit fabrication process in one embodiment starts with a semiconductor wafer substrate, and results in an IC in the form of a circuit membrane where each transistor or semiconductor device (SD) in the IC has complete dielectric isolation from every other such semiconductor device in the IC. Only interconnect at the specific electrode contact sites of the semiconductor devices provides electrical continuity between the semiconductor devices. The primary feature of the MDI process is complete electrical isolation of all semiconductor devices of an IC from all of the intervening semiconductor substrate on which or in which they were initially formed and to do so at lower cost and process complexity than existing bulk IC p
Church Craig E.
Elm Technology Corporation
Fish & Neave
Morris Robert W.
Poh Philip R.
LandOfFree
Lithography device for semiconductor circuit pattern generation does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Lithography device for semiconductor circuit pattern generation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Lithography device for semiconductor circuit pattern generation will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3240768