Lithographic offset alignment techniques for RAM fabrication

Details Lithographic offset alignment techniques for RAM fabrication Lithographic offset alignment techniques for RAM fabrication

1977-07-22

1979-03-27

Tupman, W.

Metal working

Method of mechanical manufacture

Assembling or joining

29578, 29589, 357 24, 357 91, B01J 1700

Patent

active

041458036

ABSTRACT:
Lithographic offset alignment techniques for MOS dynamic RAM memory cell fabrication to enable increased packing density while maintaining the minimum patterned geometry. Technique of cell fabrication involves initial oxidation of P-type silicon, for example, followed by silicon nitride deposition. Thereafter, moats are etched using the composite silicon dioxide-silicon nitride layers, followed by boron deposition or ion implantation in regions of the silicon substrate exposed by the etching treatment. The moats are then filled by oxidation to form a large field deposit of silicon dioxide extending above the level of the oxide layer in the regions where the moats were formed. The remaining composite silicon dioxide-silicon nitride layers are then removed, followed by gate oxidation. A P-type ion implant is provided beneath the thin oxide region between the regions to be overlaid by a polysilicon electrode and the thick field oxide of the succeeding cell. Thereafter, polysilicon is deposited and patterned, the patterned polysilicon electrode covering a fraction of the P-type implant. The gate oxide is then removed by etching, followed by N+ diffusion or ion implantation in the exposed region of the P-type implant to define a bit line having a length less than the minimum patterned geometry. Oxide is then applied by chemical vapor deposition, followed by a deposit of metal or polysilicon and patterning as required. The offset alignment of the polysilicon electrode with respect to the P-type implant creates the smaller dimension for the sense line. A fabrication technique for the CC RAM having an implanted storage region and a fabrication technique for a double-level polysilicon cell both using offset alignment techniques are also disclosed.

REFERENCES:
patent: 3913211 (1975-10-01), Seeds

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