Boots – shoes – and leggings
Patent
1984-02-16
1988-07-19
Shaw, Gareth D.
Boots, shoes, and leggings
G06F 700
Patent
active
047589477
ABSTRACT:
Disclosed is a slave processor (100) for a multiprocessor logic circuit fault simulator. The slave processor has a hardware-based list processor (110) for performing set algebra operations on fault lists (300). The operation of the list processor centers on a characteristic vector (A) that has a bit (360) for each fault number (310) that can appear in a fault list. The bits are implemented in bit locations (210) of a register (201). The list processor also has a second vector (B), implemented in a register (202), whose bit locations form shift register pairs (208) with locations of vector A bits to store values of vector A bits shifted out by entry of new values. The list processor further has two stacks (A, B), implemented in memories (203, 204), for storing fault numbers. As fault numbers of a first fault list are loaded into the list processor, corresponding vector A bits are set, and the fault numbers are pushed onto the stack A. As fault numbers of subsequent fault lists are loaded, corresponding or non-corresponding vector A bits are set or reset, depending upon whether the set operation being performed is union, intersection, or difference. Thereafter, using the bit maps of vectors A and B, values are popped from the stack A, and selectively pushed onto the stack B, to generate an output fault list. The list processor also performs comparisons between pairs of lists. The processor optionally includes a third vector (C), implemented in a register (213), and associated controls (214) for processing star fault bits of fault numbers.
REFERENCES:
Koffman, "Problem Salving and Stuctured Programming in PASCAL" 1981, pp. 264-276.
Maruyama, K., "Circuit for Conditional Substring Function", IBM Technical Disclosure Bulletin, vol. 18, No. 19, Feb. 1976, pp. 3099-3104.
Roth, J. P., "Hardware Implementation of Software", IBM Technical Disclosure Bulletin, vol. 20, No. 10, Mar. 1978, pp. 4238-4240.
Birney, R. E. et al, "List Processor", IBM Technical Disclosure Bulletin, vol 20, No. 8, Jan. 1978, pp. 2972-2974.
A. N. Tenenbaum et al. "Data Structures Using Pascal", pp. 35-36, Prentice-Hall, Inc., (1981).
R. Clark et al, "The UCSD Pascal Handbook", p. 100, Prentice-Hall, Inc., (1982).
G. W. Cherry "Pascal Programming Structures", pp. 275-283, Reston Pub. Co., Inc., (1980).
J. Duntemann "Complete Turbo Pascal", pp. 67-77, Scott, Foresman and Co., (1986).
Y. Levendel et al., "Special-Purpose Computer for Logic Simulation Using Distributed Processing", Bell System Technical Journal, vol. 61, No. 10, (Dec. 1982), pp. 2873-2909.
Y. Levendel et al., "Parallel Fault Simulation Using Distributed Processing", Bell System Technical Journal, vol. 62, No. 10, (Dec. 1983), pp. 3107-3137.
G. Pfister, "The Yorktown Simulation Engine: Introduction", Proc. 19th Design Automation Conf., Las Vegas, NV, Jun. 14-16, 1982, pp. 51-54.
M. M. Denneau, "The Yorktown Simulation Engine", Proc. 19th Design Automation Conf., Las Vegas, NV, Jun. 14-16, 1982, pp. 55-59.
E. Kronstadt et al., "Software Support for the Yorktown Simulation Engine", Proc. 19th Design Automation Conf., Las Vegas, NV, Jun. 14-16, 1982, pp. 60-64.
T. Sasaki et al., "HAL: A Block Level Hardware Logic Simulator", Proc. 20th Design Automation Conf., Miami Beach, FL, Jun. 27-29, 1983, pp. 150-156.
N. Koike et al., "A High Speed Logic Simulation Machine", Proc. Spring '83 COMPCON, Feb./Mar. 1983, pp. 446-451.
M. Abramovici et al., "A Logic Simulation Machine", Proc. 19th Design Automation Conf., Las Vegas, NV, Jun. 14-16, 1982, pp. 65-73.
D. B. Armstrong, "A Deductive Method for Simulating Faults in Logic Circuits", IEEE Trans. Comp., vol. C-21, No. 5, (May 1972), pp. 464-471.
Y. Levendel, "Some Experiments and Problems in Fault Simulation", Technical Report, Math-71, University of Negev, May 1974.
S. G. Chappell et al., "LAMP: Logic-Circuit Simulators", Bell System Technical Journal, vol. 53, No 8, (Oct. 1974), pp. 1451-1476.
H. Y. Chang et al., "Deductive Techniques for Simulating Logic Circuits", Computer, vol. 8, No. 3, (Mar. 1975), pp. 52-59.
A. Miara et al., "Dynamic and Deductive Fault Simulation", Proc. 15th Design Automation Conf., Las Vegas, NV, Jun. 19-21, 1978, pp. 439-443.
P. R. Menon et al., "Deductive Fault Simulation with Functional Blocks", IEEE Trans. Comp., vol. C-27, No. 8, (Aug. 1978), pp. 689-695.
Levendel Ytzhak
Menon Premachandran R.
Patel Suresh H.
American Telephone and Telegraph Company AT&T Bell Laboratories
Fairbanks Jonathan C.
Shaw Gareth D.
Volejnicek David
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