Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2001-09-28
2004-10-19
Chang, Kent (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S089000, C345S099000
Reexamination Certificate
active
06806860
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2000-300491, filed on Sep. 29, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a liquid crystal driving circuit in which grayscale display is possible, and a load driving circuit for selectively driving a capacitive load.
2. Related Background Art
Since there is only a limited space in a cellular phone, a large-capacitance battery cannot be mounted, and power consumption of a circuit in the phone needs to be reduced as much as possible. On the other hand, a cellular phone having a color liquid crystal panel has increased.
A conventional source driver IC for driving a liquid crystal panel has a buffer amplifier for each signal line in the panel. Therefore, the source driver IC having m pieces of driving output terminals always operate m (e.g., 384 or 420) pieces of buffer amplifiers, thereby increasing the power consumption.
FIG. 11
is a block diagram showing a schematic configuration of this type of conventional signal line driving circuit. The signal line driving circuit of
FIG. 11
includes: a shift register
1
for successively shifting a shift pulse supplied from the outside in synchronization with a transfer clock; a plurality of data latch circuits
2
for latching digital grayscale data in synchronization with the shift pulse outputted from each output terminal of the shift register
1
; a load latch circuit
3
for latching outputs of the plurality of data latch circuits
2
at the same timing; a level shifter
4
for converting a level of an output of the load latch circuit
3
; a D/A converter
5
for outputting an analog voltage in accordance with an output of the level shifter
4
; a buffer amplifier
6
for buffering an output of the D/A converter
5
; and a breeder
7
for generating an analog reference voltage corresponding to the digital grayscale data. Each output of the buffer amplifier
6
is supplied to each signal line.
Briefly, the breeder
7
divides an external voltage between two power supply voltage (Vcc and GND) by a plurality of resistors connected in series and generates the analog reference voltage.
In the conventional signal line driving circuit shown in
FIG. 11
, as one method for solving a problem that the power consumption increases, there is proposed a method of disposing the buffer amplifier for each reference voltage line for supplying the analog reference voltage, instead of disposing the buffer amplifier for each signal line. In this case, when the number of grayscales is n, 2
n
pieces of buffer amplifiers may be disposed. As compared with the buffer amplifiers disposed for the respective signal lines, the number of buffer amplifiers can largely be reduced, and the power consumption can be reduced.
FIG. 12
is a block diagram of a display apparatus disclosed in Japanese Patent Application Laid-Open No. 326084/1998, in which the buffer amplifier is disposed for each reference voltage line. The display apparatus of
FIG. 12
includes switches SW
10
to SW
25
for switching whether or not to operate each buffer amplifier, and a grayscale conversion/buffer control circuit
71
for selecting a grayscale number in accordance with an input image signal. The number of buffer amplifiers to be operated is changed in accordance with the selected grayscale number, thereby reducing the power consumption.
However, since the display apparatus of
FIG. 12
always selects the grayscale number in accordance with the input image signal, a processing burden in the grayscale conversion/buffer control circuit
71
increases. Particularly, when the input image signal frequently changes, e.g. a moving picture, the power consumption of the grayscale conversion/buffer control circuit
71
possibly increases. Moreover, a memory for storing at least one frame of input image signals is necessary, and it is difficult to miniaturize the circuit. Furthermore, the display apparatus of
FIG. 12
converts the inputted analog image signal by an A/D converter
72
, and then carries out the processing in the grayscale conversion/buffer control circuit
71
. Therefore, a high-precision A/D converter is required, thereby increasing a component cost.
For example, when the cellular phone is in a waiting state, only minimum information such as a character is preferably displayed to suppress the power consumption as much as possible. However, when the display apparatus of
FIG. 12
is used for the cellular phone, the power consumption of the grayscale conversion/buffer control circuit
71
does not decrease even in the waiting state, and as a result, a waiting time is shortened.
When the buffer amplifier
6
is disposed for each reference voltage line for supplying the analog reference voltage as shown in
FIG. 11
, it is general to constitute the buffer amplifier
6
by an operational amplifier
11
including two gain stages. Moreover, to improve stability, as shown in
FIG. 13A
, an output terminal of the output gain stage
11
is fed back to an input terminal via a capacitor element C
10
, and a phase margin is secured by Miller compensation. Alternatively, as shown in a circuit of
FIG. 14A
proposed in Japanese Patent Application Laid-Open No. 150427/1999, the phase margin is secured by performing phase compensation using a zero obtained by a resistance Rz and load capacitance C
L
connected in series to the output.
In the circuit of
FIG. 13A
, a second pole appearing in an open loop frequency characteristic depends on a frequency gm
2
/C
L
determined by a transconductance gm
2
of a second gain stage and the load capacitance C
L
as shown in a frequency characteristic diagram of FIG.
13
B. Additionally, a phase rotates by 90 degrees per pole.
In the circuit of
FIG. 13A
, the larger the load capacitance becomes, the lower the frequency of the second pole becomes, i.e. gm
2
/(m·C
L
), in accordance with the number m of loads to be driven. Therefore, even in case of a small load capacitance, the phase margin is reduced in driving m (m>>1) loads. When m is larger, there is a problem that the phase margin is further reduced, and oscillation easily occurs.
On the other hand, in the circuit of
FIG. 14A
, as shown in a frequency characteristic diagram of
FIG. 14B
, even when a load amount changes, the frequency of the second pole does not move. However, the frequencies of the first pole and the zero change in accordance with the load amount. Moreover, in the circuit of
FIG. 14A
, as the number of loads increases, a waveform becomes more dull and a settling time becomes longer by a low pass characteristic due to the resistance Rz and load capacitance m·C
L
.
SUMMARY OF THE INVENTION
According to the present invention, there is provided a liquid crystal driving circuit configured to supply an analog voltage in accordance with digital grayscale data to each of a plurality of signal lines, said circuit comprising:
a reference voltage generation circuit configured to output analog reference voltages corresponding to each of said digital grayscale data;
a plurality of buffer amplifiers configured to individually perform buffering of said respective analog reference voltages;
a grayscale mode circuit configured to determine a grayscale number of said digital grayscale data based on a grayscale mode signal supplied from the outside; and
an amplifier enable circuit configured to set each of said plurality of buffer amplifiers to an enable state or a disable state based on an output signal of said grayscale mode circuit.
Moreover, according to the present invention, there is provided a liquid crystal driving circuit configured to supply an analog voltage in accordance with digital grayscale data to each of a plurality of signal lines, said circuit comprising:
a reference voltage generation circuit configured to output analog reference voltages corresponding to each of said digital grayscale data;
a plurality of buf
Itakura Tetsuro
Minamizaki Hironori
Saito Tetsuya
LandOfFree
Liquid crystal driving circuit and load driving circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Liquid crystal driving circuit and load driving circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Liquid crystal driving circuit and load driving circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3314392