Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-04-13
2002-04-09
Hjerpe, Richard (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S100000, C345S211000
Reexamination Certificate
active
06369790
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a liquid crystal driving circuit for driving a liquid crystal display system by the multi-line selection (MLS) method, and a liquid crystal display system driven by the liquid crystal driving circuit.
2. Related Background Art
In recent years, liquid crystal display systems are widely noticed as light flat panel displays of low electric power consumption. As one of methods for driving such liquid crystal display systems, the MLS method for simultaneously selecting a plurality of scanning lines, i.e., a plurality of common electrodes connected to the scanning lines, is known. Referring to
FIGS. 9 through 16
, a conventional liquid crystal display system driven by the MLS method will be described.
FIG. 9
is a block diagram showing a typical construction of a liquid crystal display system driven by the MLS method. As shown in
FIG. 9
, the liquid crystal display system driven by the MLS method comprises a liquid crystal display part
2
, a common electrode driving circuit
10
, a segment electrode driving circuit
30
, a function generating part
50
, and a random access memory (RAM)
70
for display data.
The liquid crystal display part
2
comprises: a first transparent substrate, on which a plurality of common electrodes are arranged in parallel to each other; a second transparent substrate, on which a plurality of segment electrodes are arranged in parallel to each other, the second transparent substrate facing the first transparent substrate so that the segment electrodes intersect the common electrodes; and a liquid crystal layer sandwiched between the first and second transparent substrates. Each of the common electrodes is connected to a corresponding one of different scanning lines COMi (i=1, . . . , m), and each of the segment electrodes is connected to a corresponding one of different signal lines SEGj (j=1, . . . , n).
The common electrode driving circuit
10
is designed to simultaneously select a plurality of scanning lines to drive the common electrodes connected to the selected scanning lines.
FIG. 10
shows the details of the common electrode driving circuit
10
and the function generating part
50
. The common electrode driving circuit
10
is designed to simultaneously select four scanning lines. The common electrode driving circuit
10
comprises: a shift register
11
; a plurality of logic parts
13
, each of which is provided for each scanning line COMi (i=1, . . . , m); and a plurality of sets of three analog switches
15
,
16
and
17
, each set of which is provided for each scanning line COMi (i=1, . . . , m). The function generating part
50
has a 2-bit binary counter
51
and a function generator circuit
55
.
The 2-bit binary counter
51
is designed to operate in response to a field start signal and count the pulse number of the field start signal in synchronism with a shift clock to transmit counted values FS
1
and FS
0
to the function generator circuit
55
. The FS
0
and FS
1
are indicative of the low-order bits and high-order bits of the counted values, respectively, and also called field select signals.
The function generator circuit
55
is designed to generate 4-bit values FD
0
, FD
1
, FD
2
and FD
3
, which correspond to an alternating signal ALT and the output signals FS
1
and FS
0
of the 2-bit binary counter
51
, on the basis of these signals. For example, as shown in
FIG. 11
, when ALT=“0”, FS
1
=“0” and FS
0
=“0”, then FD
0
=FD
1
=FD
2
=FD
3
=“1”, i.e., values shown in a column
6
1
are generated, and when ALT=“0”, FS
1
=“0” and FS
0
=“1”, then FD
0
=FD
2
=“1” and FD
1
=FD
3
=“0”, i.e., values shown in a column
6
2
are generated.
Furthermore, the functions FD
0
, FD
1
, FD
2
and FD
3
shown in
FIG. 11
are called Hadamard functions. The column
6
1
is used for selecting a first field which forms one frame, and the column
6
2
is used for selecting a second field. In addition, a column
6
3
is used for selecting a third field, and a column
6
4
is used for selecting a fourth field. Moreover, columns
7
i
(i=1, . . . , 4) are formed by inverting the respective values of the column
6
i
. The column
7
1
is used for selecting the first field, and the column
7
2
is used for selecting the second field. The column
7
3
is used for selecting the third field, and the column
7
4
is used for selecting the fourth field. The use of these columns
7
1
through
7
4
prevents charges from being stored in the liquid crystal layer.
On the other hand, the shift register
11
of the common electrode driving circuit
10
is designed to sequentially select the first through fourth fields on the basis of a field start signal, and simultaneously select four successive scanning lines on the basis of a shift clock signal in each of the selected fields to sequentially carry out the simultaneous selection. For example, as shown in
FIG. 12
, when the shift register
11
receives a first field start signal, a first field is selected. Thereafter, when the shift register
11
receives a shift clock, the shift register
11
outputs a signal OA for simultaneously selecting scanning lines COM
1
through COM
4
. Then, on the basis of the next shift clock, the shift register
11
outputs a signal OB for simultaneously selecting scanning lines COM
5
through COM
8
. Thus, the operations for simultaneously selecting four successive scanning lines within a selection period for the first field are sequentially carried out.
Each of the logic parts
13
comprises two inverter gates and two AND gates. The logic part
13
corresponding to the scanning line COM
1
is designed to select one analog switch, which is connected to the scanning line COM
1
and which is one of the three analog switches
15
,
16
and
17
, on the basis of the output signal OA of the shift register
11
and the output FD
0
of the function generator circuit
55
. The logic part
13
corresponding to the scanning line COM
2
is designed to select one analog switch, which is connected to the scanning line COM
2
and which is one of the three analog switches
15
,
16
and
17
, on the basis of the output signal OA of the shift register
11
and the output FD
1
of the function generator circuit
55
.
The logic part
13
corresponding to the scanning line COM
3
is designed to select one analog switch, which is connected to the scanning line COM
3
and which is one of the three analog switches
15
,
16
and
17
, on the basis of the output signal OA of the shift register
11
and the output FD
2
of the function generator circuit
55
. The logic part
13
corresponding to the scanning line COM
4
is designed to select one analog switch, which is connected to the scanning line COM
4
and which is one of the three analog switches
15
,
16
and
17
, on the basis of the output signal OA of the shift register
11
and the output FD
3
of the function generator circuit
55
.
Similarly, each of the logic parts
13
corresponding to the scanning lines COM
5
through COM
8
is designed to select one analog switch, which is connected to the corresponding scanning line and which is one of the three analog switches
15
,
16
and
17
, on the basis of the output signal OB of the shift register
11
and the output of the function generator circuit
55
.
Each of the analog switches
15
,
16
and
17
is designed to supply a voltage Vr (≠0), 0 or −Vr to the corresponding scanning lines when it is selected by the corresponding logic part
13
.
Therefore, as shown in
FIG. 12
, when the first field is selected, if the signal OA is outputted from the shift register
11
(OA=“1”), the voltage Vr is supplied to the scanning lines COM
1
, COM
2
, COM
3
and COM
4
, so that the voltage Vr is applied to the common electrodes connected to the scanning lines COM
1
, COM
2
, COM
3
and COM
4
. Furthermore, when the signal OA is not outputted, voltage
0
is supplied to
Hjerpe Richard
Kabushiki Kaisha Toshiba
Nguyen Frances
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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