Computer graphics processing and selective visual display system – Display driving control circuitry
Reexamination Certificate
1998-06-17
2001-08-28
Saras, Steven (Department: 2675)
Computer graphics processing and selective visual display system
Display driving control circuitry
C345S098000, C345S100000
Reexamination Certificate
active
06281890
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a liquid crystal drive circuit for outputting a voltage for driving a liquid crystal, and a liquid crystal display system including the circuit.
As a device which selects one of four different voltages V
1
to V
4
for driving a liquid crystal panel and outputs the selected voltage, and to which the present invention pertains, the device shown in
FIG. 8
is known. This device comprises, e.g., 160 blocks BL
1
to BL
160
each including a shift register unit
111
for shifting an input signal IN, an output selection circuit
112
for determining the voltage to be output to the liquid crystal panel, and an output buffer
113
for outputting the voltage determined by the output selection circuit
112
.
The shift register unit
111
has a shift register including an inverter IN
51
for receiving a clock CLK and outputting an inverted clock /CLK, clocked inverters CIN
51
to CIN
54
which are enabled/disabled in response to the input clocks CLK and /CLK, and inverters IN
52
and IN
53
. When the clocked inverter CIN
51
is enabled in response to the clock CLK, the input signal IN is inverted and output. When the clocked inverter CIN
51
is disabled, the clocked inverter CIN
53
is enabled to hold the output state of the inverter IN
52
. This output is inverted by the clocked inverter CIN
52
, and is inverted again by the inverter IN
53
. When the clocked inverter CIN
52
is disabled, the clocked inverter CIN
54
is enabled to hold the output form the inverter IN
53
. The output from the inverter IN
53
is supplied to the output selection circuit
112
as an output signal Q
1
of the shift register unit
111
.
The output selection circuit
112
receives the output signal Q
1
from the shift register unit
111
, and a frame signal FR, the level of which is inverted in units of frames. Two-input NAND gates NA
61
to NA
64
receive one of the frame signal FR and its inverted signal /FR obtained via an inverter IN
71
, and one of the output from the shift register unit
111
and its inverted signal obtained via an inverter IN
72
, and respectively supply their outputs to the output buffer
113
as switching control signals SELL to SEL
4
.
The output buffer
113
receives four different voltages V
1
to V
4
, and the switching control signals SEL
1
to SEL
4
output from the output selection circuit
112
, and selects and outputs one voltage to be supplied to a liquid crystal panel (not shown) on the basis of the signals SEL
1
to SEL
4
. The switching control signals SEL
1
to SEL
4
, and signals /SEL
1
to /SEL
4
respectively inverted by inverters IN
61
to IN
64
are supplied to switching elements SW
61
to SW
64
each constituted by a combination of p- and n-MOS transistors to turn on one of these switching elements. In this way, the selected one of the four voltages V
1
to V
4
is output as an output voltage OUT
1
.
In other blocks BL
2
to BL
160
as well, the shift register units
111
generate signals Q
2
to Q
160
, and supply them to the output selection circuits
112
. The output selection circuits
112
output switching signals SEL
1
to SEL
4
, and the output buffers
113
output the selected voltages. Note that the signals Q
1
to S
160
in the shift register units
111
in the blocks BL
1
to BL
160
have shifts toward the latter stages.
The voltages V
1
to V
4
are generated by a power supply circuit shown in
FIG. 9. A
predetermined power supply voltage V
DD
and ground voltage V
ss
are supplied to a DC-DC converter
101
to generate a voltage V
GG
. The voltage V
GG
is input to an emitter-follower circuit including a resistor
102
, variable resistor
108
, and a pnp bipolar transistor
113
to output a voltage V
EE
. The potential difference between the voltages V
GG
and V
EE
is divided by the resistances of five fixed resistors
103
to
107
, and four sets of operational amplifiers
109
to
112
, resistors
114
to
117
, and capacitors
118
to
121
output stabilized voltages V
1
to V
4
.
However, the liquid crystal drive circuit shown in
FIG. 8
suffers the following problems. After the power supply is turned on and the power supply voltage stabilizes, data is input from a terminal IN, and the clock CLK is input from a clock terminal CLK. Then, the shift register units
111
are enabled to shift the data, and the values of the output signals Q
1
to Q
160
of the shift register units of all the blocks are determined. A long period of time is required from when the power supply is turned on until the values of the signals Q
1
to Q
160
are determined, and the signal values remain unknown during this interval. For this reason, whether or not the liquid crystal panel applied with one of the voltages V
1
to V
4
at its scanning electrodes is turned on is finally uncertain.
If the liquid crystal panel is turned on upon power ON, electric power is wasted during this interval. Furthermore, since an unnecessary current path is formed in the power supply circuit shown in
FIG. 9
in this case, the rise time required until the power supply voltage reaches a prescribed level is prolonged. As described above, the liquid crystal drive circuit shown in
FIG. 8
suffers the problems including an increase in consumption power and a decrease in display response speed of the liquid crystal panel.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a liquid crystal drive circuit which can prevent an increase in consumption power upon power ON, and can increase the display response speed of a liquid crystal panel, and a liquid crystal display system including the circuit.
According to the present invention, there is provided a liquid crystal drive circuit comprising a shift register unit for receiving an input signal and clock, and outputting a signal obtained by shifting the input signal on the basis of the clock, an output selection circuit for receiving the signal output from the shift register unit, and a frame signal, and outputting a switching control signal, an output buffer for receiving the switching control signal, and at least two different voltages, and selecting and outputting one of the input voltages on the basis of the switching control signal, a selection control circuit for receiving the signal output from the shift register unit, and for, when the signal has a predetermined value, determining abnormal operation and generating a selection control signal; and a clock control circuit for, when the selection control circuit generates the selection control signal, inputting a signal having a given value to the shift register unit in place of the clock to make the shift register unit operate as an inverter array.
Note that the selection control circuit may determine abnormal operation and generate a selection control signal when a predetermined one of signals output from the shift register unit assumes a value which makes the output buffer output a display voltage for setting the liquid crystal panel in a display state.
Alternatively, the selection control circuit may include an AND gate or NAND gate which receives a plurality of predetermined signals of the signals output from the shift register unit, and may output the selection control signal when all the input signals have values for making the liquid crystal panel display, the clock control circuit may include an OR gate or NOR gate for receiving the selection control signal output from the selection control circuit, and the clock, and an AND gate or NAND gate for receiving a signal obtained by inverting a polarity of the selection control signal, and the clock, and when the OR gate or NOR gate and the AND gate or NAND gate receive the selection control signal from the selection control circuit, the OR gate or NOR gate and the AND gate or NAND gate may output signals having the given value to the shift register unit.
A liquid crystal drive circuit according to the present invention comprises a first block having a first shift register unit for receiving an input signal and a clock, and outputting a signal
Anyaso Uchendu O.
Foley & Lardner
Kabushiki Kaisha Toshiba
Saras Steven
LandOfFree
Liquid crystal drive circuit and liquid crystal display system does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Liquid crystal drive circuit and liquid crystal display system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Liquid crystal drive circuit and liquid crystal display system will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2541479