Liquid crystal cells – elements and systems – Particular excitation of liquid crystal – Electrical excitation of liquid crystal
Reexamination Certificate
1999-09-14
2002-06-11
Sikes, William L. (Department: 2871)
Liquid crystal cells, elements and systems
Particular excitation of liquid crystal
Electrical excitation of liquid crystal
C349S038000, C349S042000
Reexamination Certificate
active
06404465
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a liquid crystal display provided with a thin film transistor array substrate for use in matrix type display and to a manufacturing method thereof.
2. Description of the Prior Art
Generally, a matrix type display comprises a thin film transistor array substrate (hereinafter referred to as TFT array substrate) on which a thin film transistor (hereinafter referred to as TFT) is formed, and a counter substrate on which color filter, black matrix, etc. are formed. A display material such as liquid crystal is held between the mentioned two substrates, and in which a voltage is selectively applied to the display material.
In the TFT array substrate, as shown in the equivalent circuit of
FIG. 14
, pixels are arranged forming a matrix.
In
FIG. 14
, reference numerals G
1
, G
2
, G
3
indicate scanning signal lines (hereinafter referred to as gate lines), and numerals S
1
, S
2
, S
3
indicate image signal lines (hereinafter referred to as source lines). Cs
1
, Cs
2
, Cs
3
indicate storage capacitance electrode lines for forming a storage capacitance (hereinafter referred to as Cs lines).
Further, numerals
1
a
to
1
i
indicate TFT(s), and charge and discharge of an electric charge to and from a pixel electrode is controlled using the TFT(s) as switching element(s). Numerals
2
a
to
2
i
are storage capacitances which are prepared by forming an insulating film between the pixel electrode and the Cs lines. The pixel electrode is formed to be a transparent electrode such as ITO, and forms liquid crystal capacities
3
a
to
3
i
holding a liquid crystal between itself and the counter electrode. Numerals
4
a
to
4
i
are parasitic capacities Cdp formed parasitically between the source lines and the pixel electrode. On/Off operation of the TFT is performed using the gate lines as gate electrodes.
The pixel electrode is connected to the source line through the TFT, and amount of electric charge given to the pixel electrode varies depending on signal level of the source line, whereby a potential of the pixel electrode is established. In response to a voltage between the pixel electrode and the counter electrode, amount of displacement of liquid crystal varies, and amount of a transmitted light through the backside is changed. Accordingly, by controlling the signal level of the source line, optical signal change is restrained and displayed in the form of an image.
To improve image quality, it is necessary to reduce as small as possible variation in pixel potential due to change in signal level of the gate line, etc. For that purpose, total capacity of the pixel is increased by providing the pixel electrode with the storage capacitances
2
a
to
2
i
. The storage capacitances
2
a
to
2
i
are formed by providing an insulating film between the Cs lines Cs
1
to Cs
3
of the same potential as that of the counter electrode and the pixel electrode.
FIG. 15
shows a pixel layout in the conventional TFT array substrate.
FIG. 16
shows a sectional view of a region A—A of
FIG. 15
taken in the direction of the arrows.
FIGS. 17 and 18
show a conventional method of forming a pixel section taking the sectional view of the A—A region as an example.
In
FIG. 15
, reference numeral
102
indicates a gate line, numeral
104
indicates a semiconductor thin film, numeral
107
is a source line, numeral
108
is a source electrode, numeral
109
is a drain electrode, numeral
111
is a Cs line, and numeral
114
is a pixel electrode.
In
FIG. 16
, reference numeral
101
indicates a glass substrate, and numeral
103
indicates a gate insulating film, numeral
105
is an i-layer (a semiconductor layer composed of non-doped amorphous silicon, etc.). Numeral
106
is a n-layer (for example, a semiconductor layer composed of amorphous silicon, etc. containing n-type impurity), and numeral
113
is an insulating film. Same reference numerals as those given for the above description are designated to the same or like parts.
A manufacturing process of the matrix type display having a sectional structure as shown in
FIG. 16
is hereinafter described with reference to
FIGS. 17 and 18
.
First, as shown in FIG.
17
(
a
), a metal film
102
a
to serve as the gate electrode
102
is formed on the glass substrate
101
, and then, as shown in FIG.
17
(
b
), a resist pattern
110
a
having a planar shape corresponding to the gate electrode
102
is formed thereon. Using the resist pattern
110
a
as an etching mask, an etching is applied to the metal film
102
a
, thus the gate electrode
102
is obtained, and then the resist pattern
110
a
is removed.
Then, as shown in FIG.
17
(
c
), the gate insulating film
103
, i-layer
105
, and n-layer
106
are laminated in order, and as shown in FIG.
17
(
d
), a resist pattern
110
b
is formed on the region where the i-layer
105
and the n-layer
106
are left, and using the resist pattern
110
b
as an etching mask, the n-layer
106
and the i-layer
105
are etched in order. The resist pattern
110
b
is then removed.
Subsequently, as shown in FIG.
17
(
e
), an ITO thin film
114
a
to serve as the pixel electrode
114
is further placed, and as shown in FIG.
18
(
a
), using a resist pattern
110
c
patterned into a shape corresponding to the pixel electrode
114
as an etching mask, the pixel electrode
114
is obtained by etching the ITO thin film
114
a
. The resist pattern
110
c
is then removed.
Then, as shown in FIG.
18
(
b
), a metal film
112
a
to serve as source line
107
, source electrode
108
, and drain electrode
109
is placed. And as shown in FIG.
18
(
c
), a resist pattern
110
d
corresponding to a region required to serve as source line
107
, source electrode
108
and drain electrode
109
, is patterned. Using the resist pattern
110
d
as an etching mask, the metal film
112
a
is etched, then the resist pattern
110
d
is removed, whereby the insulating film
113
is formed. As a result, a conventional matrix type display of the sectional structure shown in
FIG. 16
is obtained.
Then, structure and function of the conventional TFT is hereinafter described. With reference to the mentioned
FIG. 16
, when the pixel electrode
114
is charged with an electric charge, a voltage of about 9V is applied to the source electrode
108
, and a positive voltage of about 20V is applied to the gate. electrode
102
, whereby the TFT is turned on, and the drain electrode
109
and the pixel electrode
114
are charged approximately to 9V.
Thereafter, when potential of the pixel electrode
114
has sufficiently increased, a negative voltage of about −5V is applied to the gate electrode
102
, whereby the TFT is turned off, and the electric charge is constrained in the pixel.
In the conventional pixel structure described above, the pixel electrode
114
is connected to the source line
107
through the TFT, and potential of the pixel electrode
114
is established depending on signal level of the source line
107
. In response to the voltage between the pixel electrode
114
and the counter electrode, amount of displacement of the liquid crystal varies and the transmitted light from the backside is changed.
Accordingly, by controlling signal level of the source line
107
, optical signal change is controlled and displayed in the form of an image.
Maximum brightness of the liquid crystal display is determined by light transmittance (transmissivity of light) in the mentioned pixel, and the light transmittance becomes higher when area of the part through which light is transmitted, i.e., aperture in the pixel is larger. To achieve a liquid crystal display of high brightness, it is necessary to increase the area of aperture occupied in the area of the entire pixel (hereinafter referred to as aperture ratio).
As a method for increasing the aperture ratio, it is useful to decrease the distance between the pixel electrode
114
and the source line
107
in FIG.
15
. However, when decreasing the distance between the pixel electrode
114
and the source line
10
Nakayama Akio
Numano Yoshinori
Chowdhury Tarifur R.
Kabushiki Kaisha Advanced Display
Sikes William L.
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