Liquid crystal cells – elements and systems – Particular structure – Having significant detail of cell structure only
Reexamination Certificate
2002-12-20
2004-08-10
Kim, Robert H. (Department: 2871)
Liquid crystal cells, elements and systems
Particular structure
Having significant detail of cell structure only
C349S190000, C349S149000
Reexamination Certificate
active
06774973
ABSTRACT:
This application claims the benefit of Korean Patent Application No. P2001-83237, filed on Dec. 22, 2001, which is hereby incorporated by reference for all purposes as if fully set forth herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to liquid crystal displays, and more particularly to a line-on-glass (LOG) type liquid crystal displays that are capable of preventing deterioration of the picture caused by lack of hardening of a sealant formed on a liquid crystal display panel.
2. Discussion of the Related Art
Generally, liquid crystal displays (LCDs) use electric fields to control light transmittance characteristics of a layer of liquid crystal material. Accordingly, LCDs typically include a liquid crystal display panel having a plurality of liquid crystal cells arranged in a matrix pattern and a driver circuit for driving the plurality of liquid crystal cells to display a picture on the liquid crystal display panel.
The plurality of liquid crystal cells are arranged on the liquid crystal display panel at locations where gate lines cross data lines. Electric fields may be applied to the layer of liquid crystal material via pixel and common electrodes arranged on the liquid crystal display panel. Each pixel electrode is connected to a data line via source and drain electrodes of switching devices such as thin film transistors. Gate electrodes of each thin film transistor are connected to corresponding gate lines and allow pixel voltage signals to be selectively applied to corresponding pixel electrodes.
The driving circuit includes a gate driver for driving the gate lines, a data driver for driving data lines, a timing controller for controlling the gate driver and the data drivers, and a power converter for generating various DC voltages used in the liquid crystal display. The timing controller controls the gate and data drivers by controlling a driving timing of the gate and data drivers and by applying pixel data signals to the data driver. The power converter generates a common voltage (Vcom), a gate high voltage (Vgh) and a gate low voltage (Vgl), etc. needed in the liquid crystal display. The gate driver sequentially applies scanning signals to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal display one line at a time. The data driver supplies pixel voltage signals to each data line whenever the scanning signal is supplied to any one of the gate lines. Accordingly, LCDs control light transmittance characteristics of liquid crystal material using electric fields applied between pixel and common electrodes in accordance with pixel voltage signals specific to a liquid crystal cell.
Gate and data drivers are directly connected to the liquid crystal display panel and are integrated into a plurality of integrated circuits (ICs). Each of the gate driver ICs and data driver ICs are mounted to the liquid crystal display panel using tape carrier package (TCP) or chip on glass (COG) techniques. Further TCP-type gate and data driver ICs are connected to the liquid crystal display panel via a tape automated bonding (TAB) technique.
TCP-type gate and data driver ICs, connected to the liquid crystal display panel by the TAB technique, receive control signals and direct current (DC) voltage signals transmitted over signal lines provided on a printed circuit board (PCB). For example, each of the data driver ICs are connected to each other in series through the signal lines mounted on the data PCB, receive control signals and pixel data signal from the timing controller, and direct current voltage signals from the power converter. Gate driver ICs are connected to each other in series, via signal lines mounted on a gate PCB, receive control signals from the timing controller, and receive driving voltages from the power supply.
Driver ICs mounted on the liquid crystal display panel by a COG method are connected to each other by a line-on-glass (LOG) method. Mounted on a lower glass substrate of the liquid crystal display panel, the signal lines are formed using the LOG technique to receive control signals from the timing controller and power converter and driving voltages from the power converter.
Recently, the LOG method has been utilized when the driver ICs are connected to the liquid crystal display panel by the TAB technique. For example, the gate driver ICs are connected in series by the LOG method, thereby eliminating the gate PCB. In other words, the TAB-type gate driver ICs are connected in series through the signal lines mounted on the lower glass. In this case, one or more the LOG type signal lines, where the gate driver ICs are connected in series, overlaps with a sealant used for joining an upper and a lower substrate of the liquid crystal display panel together. However, a problem occurs as the ultraviolet UV rays irradiated for hardening the sealant is reflected by the signal lines arranged over the sealant, thereby generating a lack of hardening. Such a problem will be more particularly explained, as follows, in reference to
FIGS. 1
to
3
.
FIG. 1
illustrating a plan view structure of a related art LOG type liquid crystal display.
Referring to
FIG. 1
, the liquid crystal display includes a liquid crystal display panel
2
, a plurality of data TCPs
4
connected between the liquid crystal display panel
2
and a data PCB
8
, a plurality of gate TCPs
10
connected to the other side of the liquid crystal display panel
2
, a plurality of data driver ICs
6
mounted on each data TCP
4
, and a plurality of gate driver ICs
12
mounted on each gate TCP
10
.
Liquid crystal cells are located in the picture display area
16
at every area where the gate and data lines cross each other. A picture is displayed in accordance with a pixel voltage signals. In the outer area of the picture display area
16
are located data pads connected to the data TCP
4
, data links connecting the data pads with the data lines, gate pads connected to the gate TCP
10
, and gate links connecting the gate pads with the gate lines. Additionally, LOG type signal line group
14
located in the outer area are mounted on the lower substrate for connecting in series the gate driver ICs
12
mounted on the gate TCP
10
. For example, the LOG type signal line group
14
is located between the first data TCP
4
and the first gate TCP
10
. The LOG type signal line group supplies gate control signals and direct current voltage signals supplied from the outside via the data PCB to the first data TCP
4
to the first gate TCP
10
. Each of the signal lines included in the LOG type signal line group
14
supply direct current (DC) voltage signals, for example, gate high voltage signals (Vgh), gate low voltage signals (Vgl), common voltage signals (Vcom), and etc. Additionally, control signals such as a gate start pulse (GSP), a gate enable signal (GOE), and etc. are supplied.
The data PCB
8
supplies control and direct current voltage signals supplied from the timing controller and the power converter to the data driver IC
6
through each signal line. Also, the data PCB
8
supplies control signals and direct current voltage signals from the timing controller to the gate driver IC
12
to the first data TCP
4
through each signal line.
The data TCP
4
is electrically connected to the data pads provided at the upper part of the liquid crystal display panel
2
and the data TCP
4
is electrically connected to the output pads provided at the data PCB
8
. The data driver ICs
6
convert the pixel data signals (digital signals) into pixel voltage signals (analog signals) to supply to data lines on the liquid crystal display panel
2
.
The gate TCP
10
is electrically connected to the gate pads provided at one side of the liquid crystal display panel. The gate driver ICs
12
respond to input gate signals, for example, gate high voltage signals (Vgh) sequentially supplied to the gate lines. Also, gate driver ICs
12
supply the gate low voltage signals (Vgl) to the gate lines in the other periods except the period when the gate h
Kim Robert H.
LG.Philips LCD Co. , Ltd.
McKenna Long & Aldridge LLP
Nguyen Hoan C.
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