Electrophotography – Image formation – Simultaneous charging and exposure
Reexamination Certificate
2002-03-06
2004-04-06
Ton, Toan (Department: 2871)
Electrophotography
Image formation
Simultaneous charging and exposure
C399S158000
Reexamination Certificate
active
06718149
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a liquid crystal display panel and, more particularly, to a liquid crystal display panel having a wiring pattern formed in the peripheral area thereof.
DESCRIPTION OF THE RELATED ART
A typical example of the liquid crystal display has a pair of transparent substrate structures. A sealing layer keeps the transparent substrate structures spaced from each other, and liquid crystal fills the space between the transparent substrate structures. Conductive electrodes and thin film transistors are formed on the inner surface of at least one of the transparent substrate structures, and formed a matrix of pixels together with the liquid crystal. Both inner surfaces are covered with orientation films. Each of the orientation films was rubbed in a predetermined direction. The rubbing lines in the orientation films cause the liquid crystal molecules property oriented. Signal terminals and signal lines are further formed on the transparent substrate structure together with the conductive electrodes, and signals are selectively supplied through the terminals and signal lines to the electrodes. When the signals reaches selected electrodes, local electric fields are created in the liquid crystal, and makes the associated pixels transparent. Then, the light passes the transparent pixels, and forms a picture.
FIG. 1
shows the inner surface of the aforementioned substrate structure. Reference numeral
21
designates a glass substrate, and the inner surface is divided into an image-forming area
30
a
and a frame area
30
b
.
FIG. 2
shows a part of the frame area
30
b.
The image-forming area
30
a
is assigned to the matrix of pixels and the signal lines, and the frame-area
30
b
is assigned to a common line
29
, terminal blocks
31
1
to
31
3
,
32
1
to
32
3
,
33
1
to
33
3
and common terminals
36
and connectors
35
a1
,
35
a2
,
35
b1
,
35
b2
,
37
a1
,
37
a2
,
37
b1
,
37
b2
,
38
a1
,
38
a2
,
38
b1
and
38
b2
. The common line
29
extends along a pair of the side lines of the glass substrate
21
and one of the end lines, and the three portions of the common line
29
are labeled with
29
a
,
29
b
and
29
c
, respectively.
One of the connectors
35
a1
and the associated terminal block are enlarged in FIG.
2
. The connector
35
a1
is formed of non-transparent conductive material, and occupies a triangle area. The connectors
35
a1
,
35
a2
,
35
b1
,
35
b2
,
37
a1
,
37
a2
,
37
b1
,
37
b2
,
38
a1
,
38
a2
,
38
b1
, and
38
b2
occupy a wide area so that the resistance is reduced. The non-transparent triangle connectors
35
a1
,
35
a2
,
35
b1
,
35
b2
,
37
a1
,
37
a2
,
37
b1
,
37
b2
,
38
a1
,
38
a2
,
38
b1
and
38
b2
further serve as a photo-shield. The connector
35
a1
is connected at the outer end thereof to the common terminals
36
and at the inner end thereof to the common line
29
a
. Signal terminals
34
are formed on both sides of the common terminals
36
, and are assigned to a scanning signal. The signal terminals
34
are connected to the scanning lines
22
through interconnections
22
a
, and the scanning lines
22
extend in parallel to one another across the central area
30
a
. Data lines
23
extend in parallel to one another across the central area
30
a
in a direction perpendicular to the scanning lines
22
. Only one data line
23
is shown in FIG.
2
.
The pixels are arranged in rows and columns, and each pixel is designated by reference numeral
24
. The pixel
24
is equivalent to a series combination of the thin film transistor
26
and a parallel combination of capacitors
25
/
28
. The capacitor
25
represents a piece of liquid crystal between a pixel electrode and a common electrode, and the other capacitor
28
is called as “common storage”. The scanning lines
22
are connected to the gate electrodes of the thin film transistors
26
in the rows of pixels
24
, respectively, and the data lines
23
are connected to the drain nodes of the thin film transistors
26
in the columns of pixels
24
, respectively.
When a picture is to be produced in the matrix of pixels
24
, the scanning lines
22
are sequentially changed to an active level, and an image-carrying signal is synchronously supplied through the data lines
23
to the rows of pixels
24
. The pixels
24
selectively become transparent, and back light passes through the transparent pixels
24
so that the picture is produced on the matrix of pixels
24
.
As described hereinbefore, the sealing layer
10
a
extends in the frame area
30
b
, and the matrix of pixels
24
is converted with the orientation layers
11
a
. The sealing layer
10
a
passes on the non-transparent triangle connectors
35
a1
,
35
a2
,
35
b1
,
35
b2
,
37
a1
,
37
a2
,
37
b1
,
37
b2
,
38
a1
,
38
a2
,
38
b1
and
38
b2
, and the periphery of the orientation layer
11
a
reaches the non-transparent triangle connectors
35
a1
,
35
a2
,
35
b1
,
35
b2
,
37
a1
,
37
a2
,
37
b1
,
37
b2
,
38
a1
,
38
a2
,
38
b1
and
38
b2
.
The sealing layer
10
a
is to have a predetermined width and pass a predetermined route in the peripheral area
30
b
. If the sealing layer
10
a
is too narrow or deviated from the predetermined route, the liquid crystal is liable to be leaked. On the other hand, the orientation layer
11
a
is to be well aligned with the matrix of pixels
24
. If the orientation layer is offset from the matrix of pixels
24
, the liquid crystal is not properly oriented, and a picture produced thereon is degraded.
In the circumstances, it is proposed to form a vernier in the frame area. A vernier is disclosed in Japanese Patent Application laid-open No. 8-106100, and the manufacturer checks the vernier to see whether or not the sealing layer is properly routed in the frame area. Another vernier is disclosed in Japanese Patent Application laid-open No. 11-024079, and the manufacturer checks the vernier to see whether or not the orientation layer is well aligned with the matrix of pixels. Thus, the vernier is preferable from the view point of high reliability of the products.
However, the prior art verniers require additional areas in the frame areas, and the frame areas are widened. The narrower the frame area, the wider the image-forming area. For this reason, the vernier is not preferable from the view point of the wide image-forming area.
SUMMARY OF THE INVENTION
It is therefore an important object of the present invention to provide a liquid crystal display panel, which is highly reliable without sacrifice of the image-forming area.
The present inventors contemplated the problem inherent in the prior art liquid crystal display panels, and noticed that the vernier was to be formed in the connectors. First, the inventors removed the non-transparent substance from a generally rectangular area
36
a
in the connector
35
a1
, and formed a positive vernier
2
in the rectangular area
36
a
as shown in FIG.
3
. The graduations
2
a
and numerals “+1”/“0”/“−1” were non-transparent so that there remains wide transparent area
36
b
in the generally rectangular area
36
a
inside the connector
35
a1
. The graduations
2
a
are convenient to the manufacturer in order to specify the route occupied by a seal layer
11
. In this instance, the seal layer
11
had the width from +0.5 to −0.5, and the manufacturer would make the decision that the seal layer
11
was properly formed. The positive vernier
2
was formed inside the connector
35
a1
, and any additional area was not required for the positive vernier
2
.
However, the positive vernier
2
was causative of large resistance due to the narrow portions
36
c
in the connector
35
a1
. Moreover, the back light passed through the wide transparent area
36
b
, and undesirably penetrated into the image-forming area. The large resistance was causative of cross-taking and irregular brightness. The leaked light caused the picture to be in irregular brightness. In this situation, the inventors concluded that, although verniers formed inside the connectors reduced the
Shiga Syunsuke
Watanabe Makoto
Dickstein Shapiro Morin & Oshinsky LLP.
NEC LCD Technologies, Ltd
Ton Toan
LandOfFree
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