Electricity: measuring and testing – Impedance – admittance or other quantities representative of... – Lumped type parameters
Reexamination Certificate
2002-11-20
2004-08-24
Zarneki, David A. (Department: 2829)
Electricity: measuring and testing
Impedance, admittance or other quantities representative of...
Lumped type parameters
Reexamination Certificate
active
06781403
ABSTRACT:
This application claims the benefit of Korean Patent Application No. 2001-81564, filed on Dec. 20, 2001, which hereby incorporated by reference for all purposes as if fully set forth herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a liquid crystal display, and more particularly to a liquid crystal display panel of line on glass (LOG) type that is adapted to test any short imperfections of LOG-type patterns provided on the liquid crystal display panel.
2. Description of the Related Art
Generally, a liquid crystal display (LCD) controls a light transmittance of a liquid crystal using an electric field to display a picture. For example, the LCD includes a liquid crystal display panel having liquid crystal cells arranged in a matrix type, and a driving circuit for driving the liquid crystal display panel.
In a conventional liquid crystal display panel, gate lines and data lines are arranged in such a manner to cross each other. The liquid crystal cell is positioned at each area where the gate lines cross the data lines. The liquid crystal display panel is provided with a pixel electrode and a common electrode for applying an electric field to each of the liquid crystal cells. Each pixel electrode is connected, via source and drain electrodes of a thin film transistor acting as a switching device, to any one of data lines. The gate electrode of the thin film transistor is connected to any one of the gate lines allowing a pixel voltage signal to be applied to the pixel electrodes for each one line.
The driving circuit includes a gate driver for driving the gate lines, a data driver for driving the data lines, a timing controller for controlling the gate driver and the data driver, and a power supply for supplying various driving voltages used in the LCD. The timing controller controls a driving timing of the gate driver and the data driver and applies a pixel data signal to the data driver. The power supply generates driving voltages such as a common voltage Vcom, a gate high voltage Vgh and a gate low voltage Vgl, etc. The gate driver sequentially applies a scanning signal to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal display panel one line by one line. The data driver applies a data voltage signal to each of the data lines when the gate signal is applied to any one of the gate lines. Accordingly, the LCD controls a light transmittance by an electric field applied between the pixel electrode and the common electrode in accordance with the pixel voltage signal for each liquid crystal cell, to thereby display a picture.
The data driver and the gate driver directly connected to the liquid crystal display panel are integrated into a plurality of integrated circuits (ICs). Each data drive IC and gate drive IC are mounted in a tape carrier package (TCP) for connection to the liquid crystal display panel by a tape automated bonding (TAB) system, or mounted onto the liquid crystal display panel by a chip on glass (COG) system.
The drive ICs connected to each other, via the TCP, and to the liquid crystal display panel by the TAB system receive control signals and direct current voltage signals inputted from the exterior over signal lines mounted onto a printed circuit board (PCB) connected to the TCP. More specifically, the data drive ICs are connected, in series to each other, via signal lines mounted onto the data PCB, and commonly receive control signals from the timing control signal, a pixel data signal and driving voltages from the power supply. The gate drive ICs are connected, in series, via signal lines mounted onto the gate PCB, and commonly receive control signals from the timing controller and driving voltages from the power supply.
The drive ICs mounted onto the liquid crystal display panel by the COG system, are connected to each other by a line on glass (LOG) system in which signal lines are mounted on the liquid crystal display panel, at a lower glass, and receive control signals from the timing controller and the power supply and driving voltages.
Recently, even when the drive ICs are connected to the liquid crystal display panel by the TAB system, the LOG system has been employed to eliminate the PCB, thereby permitting the manufacture of a thinner liquid crystal display.
Particularly, signal lines connected to the gate drive ICs requiring relatively small signal lines are provided on the liquid crystal display panel by the LOG system eliminate the need for the gate PCB. In other words, the gate drive ICs of TAB system are connected, in series, to each other over signal lines mounted onto the lower glass of the liquid crystal display panel, and commonly receive control signals and driving voltage signals, which are hereinafter referred to as “gate driving signals”.
For instance, as shown in
FIG. 1
, is a conventional liquid crystal display omitting the gate PCB by utilizing LOG-type signal wiring includes a liquid crystal display panel
1
, a plurality of data TCP's
8
connected between the liquid crystal display panel
1
and a data PCB
12
, a plurality of gate TCP's
14
connected to other side of the liquid crystal display panel
1
, data drive ICs
10
mounted in the data TCP's
8
, and gate drive ICs mounted in the gate TCP's
14
.
The liquid crystal display panel
1
includes a lower substrate
2
provided with various signal lines and a thin film transistor array, an upper substrate provided with a color filter array, and a liquid crystal injected between the lower substrate
2
and the upper substrate
4
. Such a liquid crystal display panel
1
is provided with a picture display area
21
that consists of liquid crystal cells provided at intersections between gate lines
20
and data lines
18
for the purpose of displaying a picture. At the outer area of the lower substrate
2
, located at the outer side of the picture display area
21
, data pads extended from the data lines
18
, and gate pads extended from the gate lines
20
, are positioned. Further, a LOG-type signal line group
26
, for transferring gate-driving signals applied to the gate drive IC
16
, is positioned at the outer edge area of the lower substrate
2
.
The data TCP
8
supports the data drive IC
10
, and is provided with input pads
24
and output pads
25
electrically connected to the data drive IC
10
. The input pads
24
of the data TCP
8
are electrically connected to the output pads of the data PCB
12
while the output pads
25
thereof are electrically connected to the data pads on the lower substrate
2
. Furthermore, the first data TCP
8
is further provided with a gate driving signal transmission group
22
electrically connected to the LOG-type signal line group
26
on the lower substrate
2
. This gate driving signal transmission group
22
applies gate driving signals from the timing controller and the power supply, via the data PCB
12
, to the LOG-type signal line group
26
.
The data drive ICs
10
convert digital pixel data signals into analog pixel voltage signals to apply them to the data lines
18
on the liquid crystal display panel.
Similarly, the gate TCP
14
supports a gate drive IC
16
, and is provided with a gate driving signal transmission line group
28
electrically connected to the gate drive IC
16
and output pads
30
. The gate driving signal transmission line group
28
is electrically connected to the LOG-type signal line group
26
on the lower substrate
2
while the output pads
30
are electrically connected to the gate pads on the lower substrate
2
.
Each gate drive IC
16
sequentially applies a scanning signal being a gate high voltage signal Vgh to a gate line
20
in response to input control signals. Further, the gate drive IC
16
applies a gate low voltage signal Vgl to the gate line
20
in the remaining interval when the gate high voltage signal Vgh is not supplied.
As shown in
FIG. 2
, a conventional LOG-type signal line group
26
usually consists of signal lines for supplying direct current voltage signals such as a gate high v
LG.Philips LCD Co. , Ltd.
McKenna Long & Aldridge LLP
Nguyen Tung X.
Zarneki David A.
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