Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1997-12-30
2001-02-06
Saras, Steven J. (Department: 2775)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S096000, C345S094000
Reexamination Certificate
active
06184855
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a driver for a liquid crystal display (LCD), more panel particularly to an analog LCD driver for performing HV inversion or H inversion, and one or two sided drive.
BACKGROUND ART
Source drivers for driving a TFT (Thin Film Transistor)/LCD panel are of digital type and of analog type. According to the digital type, luminosity data corresponding to each pixel is delivered to a driver as a digital value and the driver latches the digital value and outputs the voltage corresponding to it. Methods for outputting the voltage are a switch scheme and a digital analog conversion (DAC) scheme. The switch scheme is performed by selecting and outputting one of a plurality of reference voltages. A driver using this scheme, can employ 4 bits (16 gradations) or 6 bits (64 gradations) requiring, but 16 or 64 switches for each output of the driver. It is impractical to implement gradations of more than 6 bits. The DAC scheme is performed by preparing a DAC for each output of the driver converting the received luminosity data into an analog value output. Disadvantages of this scheme are that it requires a large sized circuit and it is difficult to equate the performance of DAC provided for each output.
The output voltage of such a digital driver normally ranges from 0 V to 5 V. To cope with an LCD that is alternately driven between 0 V and 6 V and between 0 V and −6 V, a scheme of common inversion drive is adopted. This common inversion drive, changes the voltage of the common electrode of the LCD panel at a predetermined period (AC drive) as a result, the output of the driver appears to cover in the range of 1 V to 6 V and that of −1 V to −6 V (the range of 1 V to −1 V is a non-sensitive band). The period for which the voltage of this common electrode can be AC-driven is limited to the period of a horizontal sync. signal (H period). With this H inversion scheme, since a cross talk takes place in the horizontal direction of the screen, the deterioration of the screen presentation is inevitable.
With the analog type, conversion is not performed in each driver, luminosity data corresponding to each pixel is delivered to a driver in an analog value and the analog value is held in a sample hold circuit and outputted through a buffer amplifier. Since the analog type allows voltages of −6 V to 6 V can be outputted as a matter of course, it is unnecessary to perform the common inversion drive. While use of a high withstand voltage element leads to an increase in the size of each element, with proper circuit design, there is a good possibility that the total size can be made smaller than that of the digital driver. Furthermore, because of being able to cope with an infinite levels of gradations using the same circuit independently of the number of gradations, the analog driver is fit to implement more 256 gradations (full color). In addition, since it is not required to perform a common inversion drive, the HV inversion drive scheme which performs opposite-polarity write to neighboring pixels is implementable. Furthermore since no cross talk takes place, a high-quality image can be displayed.
While this, the analog type provides a high quality image, however significant design effort is required to suppress the variation of outputs and the occurrence of errors to sufficiently low limits. Furthermore, an output amplifier with a large power consumption is needed. As mentioned above, this is because outputs of from −6 V to 6 V are needed.
Accordingly, analog drivers have thus far not been utilized often for purposes having stringent requirements for power consumption, such as the display of a notebook PC, where used most of them have been large-sized drivers for high resolution displays, such as XGA or SVGA in a way to drive the source line of the LCD panel from the top and the bottom of the panel. In Published Unexamined Patent Application No. 6-295162, a scheme of driving by the two-side drive method is described.
SUMMARY OF THE INVENTION
It is one object of the present invention, therefore, to provide an LCD panel driver enabling the use of H inversion and HV inversion and enabling one and two-sided drive.
It is another object to reduce the power consumption in the analog LCD driver.
To attain these objects, one aspect of LCD panel driver comprises: a plurality of sample hold and buffer amplification units for positive input each including a sample hold circuit for sampling and holding an input video signal having a positive polarity in response to a first control signal (−SPP) and having a buffer amplifier activated during the holding for charging a data line in an LCD panel; a plurality of sample hold and buffer amplification units for negative input each including a sample hold circuit for sampling and holding an input video signal having a negative polarity in response to a second control signal (+SPN) and having a buffer amplifier activated during the holding for discharging a data line in an LCD panel; an output selector for selecting one of the buffer amplifiers in a group including one of the plurality of sample hold and buffer amplification units for a positive input and one of the plurality of sample hold and buffer amplification units for a negative input in response to a third control signal (B_SelP & N), wherein the output selector has means for connecting the data line to a common voltage while no buffer amplifier is selected; a bidirectional register for generating sampling pulses; and a controller for generating the first and second control signals which control the timing of sampling and holding in the sample hold circuits and the third control signal from a mode specification signal specifying whether one-side drive or two-side drive, and HV inversion or H inversion, a fourth control signal created in response to a Horizontal sync. signal and Vertical sync. signal to control the polarity of output voltage to the LCD panel and the sampling pulses.
A user using this LCD panel driver inputs a mode specification signal directing whether one-side drive or two-side drive, and HV inversion or H inversion is performed. Using this mode specification signal and the fourth control signal created by the external controler from a Horizontal sync. (HS) signal and Vertical sync. (VS) signal, the third control signal used in the output selector and the first and second control signal used in sample hold and buffer amplification units for a positive input and for a negative input are provided. In this manner, a wide variety of user's requests can be accommodated.
In addition, the sample hold and buffer amplification units are divided into those for positive inputs and those for the negative inputs, and those sample hold and buffer amplification units are selected by the first and second control signal. Therefore the drive of buffer amplifiers is cut in half. Futhermore, an output of the operating sample hold and buffer amplification unit selected by the third control signal is arranged so as to be outputted to the data line (source line) of the LCD panel during the period for which neither half of them is selected, the data line is connected to the common voltage. Accordingly the power consumption in the buffer amplifiers is reduced.
Another aspect of the present invention comprises: a plurality of sample hold and buffer amplification units for positive input each including a sample hold circuit for sampling and holding an input video signal having a positive polarity in response to a first control signal (−SPP) and having a buffer amplifier activated during the holding for charging a data line in an LCD panel; a plurality of sample hold and buffer amplification units for negative input each including a sample hold circuit for sampling and holding an input video signal having a negative polarity in response to a second control signal (+SPN) and having a buffer amplifier activated during the holding for discharging a data line in an LCD panel; an output selector for selecting one of the buf
Kobayashi Yoshinao
Kuroda Akihiro
Sakaguchi Yoshitami
International Business Machines Corportion
Saras Steven J.
Spencer William
Tassinari R. P.
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