Liquid crystal cells – elements and systems – Particular excitation of liquid crystal – Electrical excitation of liquid crystal
Reexamination Certificate
1997-07-11
2002-11-05
Sikes, William L. (Department: 2871)
Liquid crystal cells, elements and systems
Particular excitation of liquid crystal
Electrical excitation of liquid crystal
C349S054000
Reexamination Certificate
active
06476882
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a Liquid-Crystal Display (LCD) and more particularly, to an active-matrix addressing LCD panel including a Thin-Film Transistor (TFT)-array substrate, and a method of repairing any breaking or disconnection in the source/drain bus lines arranged on the TFT-array substrate.
2. Description of the Prior Art
A TFT-array substrate of an LCD panel has a large number of TFTs, a large number of bus lines for the TFTs, and their relating components or members. However, only one of the TFTs and its neighboring bus lines and components or members are explained in this specification and or drawings attached for the sake of simplification of description.
A conventional method of fabricating a TFT-array substrate of an LCD panel is shown in
FIGS. 1A
to
1
D.
First, a metal layer (not shown), which is typically made of a metal such as chromium (Cr), molybdenum (Mo), or aluminum (Al), or their alloy, is formed on a glass plate
102
to have a thickness of several hundreds nanometers. A photoresist is coated on the metal layer thus formed by spin coating, thereby forming a photoresist layer (not shown) on the metal layer.
The photoresist layer is exposed selectively to light using a mask (not shown) with a specific pattern and then, is developed using an alkaline aqueous solution. This, the pattern on the mask is transferred onto the photoresist layer.
Subsequently, using the patterned photoresist layer as a mask, the underlying metal layer is selectively etched to form a gate bus line
110
, a rectangular gate electrode
111
, and rectangular light-shielding layers
150
and
151
on the glass plate
102
, as shown in FIG.
1
A.
The gate electrode
111
is formed to be integrated with the gate bus line
110
. The light-shielding layer
150
and
151
, which are located apart from each other, are separated from the gate bus line
110
. After the etching process is completed, the patterned photoresist layer is removed.
The light-shielding layers
150
and
151
are provided on the TFT-array substrate for the purpose of increasing the aperture ratio of the LCD panel.
Further, an insulating layer (not shown) with a thickness of several hundreds nanometers is deposited on the glass plate
102
to cover the gate bus line
110
, the gate electrode
111
, and the light-shielding layers
150
and
151
by Chemical Vapor Deposition (CVD). A part of the insulating layer, which overlaps with the underlying gate electrode
111
, serves as a gate insulating layer of a TFT Tr.
An amorphous silicon (Si) layer (not shown) with a thickness of several hundreds nanometers is formed on the insulating layer thus deposited by a CVD process. The amorphous silicon layer is then patterned to form a semiconductor island
130
. The amorphous silicon layer is entirely overlapped with the underlying gate electrode
111
, as shown in FIG.
1
B.
Using the same way as that in the previous step of forming the gate bus line
110
, a drain bus line
120
and a rectangular drain electrode
126
are formed on the insulating layer by a patterned metal layer with a thickness of several hundreds nanometers, as shown in FIG.
1
C. The drain bus line
120
extends perpendicular to the gate bus line
110
and runs through the space between the light-shielding layers
150
and
151
. The drain bus line
120
is partially overlapped with the underlying light-shielding layers
150
and
151
through the insulating layer.
The drain electrode
126
is formed to be integrated with the drain bus line
120
in the vicinity of the intersection of the gate and drain bus lines
110
and
120
. The drain electrode
126
is overlapped with the underlying gate electrode
111
through the insulating layer. The end of the drain electrode
126
is contacted with the semiconductor island
130
.
A transparent, conductive layer (not shown) with a thickness of several tens nanometers, which is made of Indium Tin Oxide (ITO) or the like, is deposited on the insulating layer by sputtering. The transparent, conductive layer is patterned by photolithography and etching to form a transparent pixel electrode
140
and a source electrode
141
on the insulating layer, as shown in FIG.
1
D. The pixel electrode
140
is partially overlapped with the underlying light-shielding layer
150
through the insulating layer. The pixel electrode
140
is located in a pixel area defined by the adjoining two gate bus lines
110
and the adjoining two drain bus lines
120
so as to be apart from these gate bus lines
110
and these drain bus lines
120
.
The source electrode
141
is formed to be integrated with the pixel electrode
140
in the vicinity of the intersection of the gate and drain bus lines
110
and
120
. The source electrode
141
is overlapped with the underlying gate electrode
111
through the insulating layer. The end of the source electrode
141
is contacted with the semiconductor island
130
.
The TFT Tr is formed by the gate electrode
111
, the gate insulating layer, the drain electrode
126
, and the source electrode
141
.
The TFT-array substrate thus fabricated is then coupled with a color-filter substrate (not shown) so as to make a fixed small gap therebetween. A liquid crystal is then filled in the gap. Thus, the LCD panel is finished.
Fabrication yield improvement is the most important problem to be solved in LCD fabrication. The fabrication yield tends to decrease due to various causes. “Bus-line breaking or disconnection”, which is a typical one of the causes, gives a large effect to the fabrication yield because only one bus-line breaking or disconnection occurring in a LCD panel leads to a “line defect”, making the whole LCD panel defective.
Accordingly, to reduce the percent defective due to bus-line breaking, a lot of improved structures have been developed.
An improved structure is disclosed in the Japanese Non-Examined Patent Publication No. 5-19294 published in January 1993, which is schematically shown in FIG.
2
. In
FIG. 2
, the same reference numerals as those in
FIGS. 1A
to
1
D are attached to the corresponding elements and therefore, the description relating to the same or corresponding elements is omitted here for simplification.
As shown in
FIG. 2
, in the same level as that of the gate bus line
110
and the protruding gate electrode
111
, a first conductive layer
112
with a rectangular shape is formed on the glass substrate
102
to be apart from the gate bus line
110
. The first conductive layer
112
is located at a position to be partially overlapped with the overlying pixel electrode
140
.
In the same level as that of the drain bus line
120
and the protruding drain electrode
126
, a protruding part
125
with a rectangular shape is formed on the insulating layer to be integrated with the drain bus line
120
. Further, a second conductive layer
127
with a rectangular shape and a source electrode
128
with a rectangular shape are formed on the insulating layer in the level of the drain bus line
120
. The second conductive layer
127
is located at a position to be partially overlapped with the underlying first conductive layer
112
and the overlying pixel electrode
140
. The source electrode
128
is contacted with the underlying semiconductor island
130
and the overlying pixel electrode
140
.
If a breaking or disconnection
60
occurs in the drain bus line
120
, a laser beam is irradiated to (a) an overlapped area
170
of the protruding part
125
of the line
120
with the underlying first conductive layer
112
, (b) an overlapped area
171
of the second conductive layer
127
with the underlying first conductive layer
112
and the overlying pixel electrode
140
, (c) an overlapped area
172
of the drain electrode
126
with the underlying gate electrode
111
, (d) an overlapped area
173
of the source electrode
128
with the underlying gate electrode
111
, respectively. Thus, the upper and lower layers or regions are electrically connected to each other at the overlapped areas
170
,
171
,
172
, and
Choate Hall & Stewart
NEC Corporation
Nguyen Dung
Sikes William L.
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