Computer graphics processing and selective visual display system – Display driving control circuitry – Display power source
Reexamination Certificate
1998-06-25
2001-09-18
Shalwala, Bipin (Department: 2678)
Computer graphics processing and selective visual display system
Display driving control circuitry
Display power source
C340S870030
Reexamination Certificate
active
06292182
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a circuit for driving liquid crystal display module (LCM), and more particularly to a LCM driving circuit for generating signals for test of LCMS. In particular, the invention relates to an LCM driving circuit for generating signals for pattern display used in a module assembly in-line in aging test and panel test for measuring reliability of LCMs.
In general, the prior LCM driving circuit has been designed so as to drive only the LCM of the predetermined mode. Therefore, in case where the mode of LCM is changed, because the LCD driving circuit suitable to the predetermined mode must be designed and then manufactured anew, it is very poor economy. The prior LCM driving circuit has driven LCM to display only fixed black pattern as a test pattern on a liquid crystal display(LCD) panel in aging test. That is, during the aging test, the prior LCM driving circuit generates the driving signals for displaying one fixed black pattern to drive the LCM, thereby resulting in displaying only black pattern on the LCD panel. Accordingly, it is impossible for the prior driving circuit to generate driving signals for display alternately black and white patterns at intervals of the desired period, for example at intervals of 2 to 3 seconds on the LCD panel during aging test. Furthermore, the prior driving circuit for aging test is not capable of providing power supply of 3.3V to LCM having use for power supply of 3.3V.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a LCM driving circuit which generates driving signals for displaying a pattern for aging test regardless of a LCM operation mode.
Another object of the present invention is to provide a LCM driving circuit applicable to an enable mode and a synchronous mode.
Yet another object of the present invention is to provide a LCM driving circuit capable of providing power supply of 3.3V or 5V to a LCM.
A further object of the present invention is to provide a LCM driving circuit which generates driving signals capable of displaying black and white patterns at intervals of a desired period.
According to an aspect of the present invention, there is provided a circuit for driving a LCM, comprising: a power supply portion for receiving an external voltage of 12V to generate internal voltages of 3.3V and 5V; a clock generation portion for generating a clock signal of desired frequency; a driving signal generation portion for receiving the clock signal from the clock generation portion to generate driving signals of a data enable signal, a horizontal synchronous signal, a vertical synchronous signal, an enable signal; a signal selection portion for selecting the desired signals of the driving signals from the driving signal generation portion and outputting the selected driving signals and the clock signal from the clock generation portion; a state detection portion for receiving the vertical synchronous signal and the external voltage of 5V to detect a normal operation state of the LCM; a power selection portion for selecting one of an external voltage of 5V and the external voltage of 12V in accordance with application of the internal voltage of 5V; and an output portion for outputting the selected driving signals and clock signal from the signal selection portion, the selected power voltage from the power selection portion, the clock signal from the clock generation portion and a state detection signal from the state detection portion.
The LCM driving circuit further comprises a circuit protection portion for protect the driving circuit by selecting an external voltage when the external voltage and an internal voltage are simultaneously applied to the driving circuit, which includes a first protection portion for selecting the external voltage of 12V when the internal voltage of 12V and an external voltage of 12V are simultaneously applied and a second protection portion for selecting the external voltage of 5V when the external voltage of 5V and the internal 5V are simultaneously applied.
The clock generation portion generates a clock signal having one of 25.175 MHz, 40 MHz or 65 MHz. The power supply portion includes a first generation portion for receiving the external voltage of 12V to generate the internal voltage of 5V; and a second generation portion for receiving the external voltage of 12V to generate the internal voltage of 3.3V.
The driving signal generation portion includes a counting portion for counting the clock signal from the clock generation portion; a data enable signal generation portion for receiving outputs of the counting portion to generate the data enable signal; a horizontal synchronous signal generation portion for receiving the data enable signal from the data enable signal generation portion to generate the horizontal synchronous signal; a vertical synchronous signal generation portion for receiving the data enable signal from the data enable signal generation portion to generate the vertical synchronous signal; an enable signal generation portion for receiving the data enable signal from the data enable signal generation portion and the vertical synchronous signal from the vertical synchronous signal generation portion to generate the enable signal; and a power stabilizing portion for stabilizing the internal voltage of 5V from the power supply portion which is provided to the data enable signal generation portion, the vertical synchronous signal generation portion and the horizontal synchronous signal generation portion.
The signal selection portion includes a transfer portion for transferring the driving signals from the driving signal generation portion and the clock signal from the clock generation portion; and a selection portion for selecting the desired signals of the driving signals from the driving signal generation portion according to operation mode of the LCM to be transferred to the output portion.
The power selection portion includes a first selection portion for providing the external voltage of 5V to the output portion in accordance with application of the internal voltage of 5V from the power supply portion; and a second selection portion for providing the external voltage of 12V to the output portion in accordance with application of the internal voltage of 5V. The first selection portion is comprised of an inverter for detecting application of the internal voltage of 5V from the power supply portion; a first transistor for providing the external voltage of 5V to the output portion according to detection result of the inverter; and a first and second resistors for supplying the external voltage of 5V to a base and collector of the first transistor, respectively. The second selection portion is comprised of a third and fourth resistors for dividing the internal voltage of 5V from the power supply portion; and a second transistor for providing the external voltage of 12V to the output portion in accordance with the divided voltage.
The state detection portion is comprised of an AND gate for receiving the vertical synchronous signal from the driving signal generation portion and the internal voltage of 5V from the power supply portion to detect the normal operation state of the LCM; and a transistor for providing a voltage of V in normal operation or the external voltage of 12V in abnormal operation to the output portion in accordance with an output of the AND gate.
According to another aspect of the present invention, there is provided to a circuit for driving a LCM, comprising: a power supply portion for receiving an external voltage of 12V to generate internal voltages of 3.3V and 5V; a clock generation portion for generating a clock signal CLK of 65 MHz and an inverted clock signal; a driving signal generation portion for receiving the clock signal from the clock generation portion to generate driving signals of a data enable signal of 800 CLK, a vertical synchronous signal of 600 H, an enable signal; a signal selection portion for selecting the desired signals of the driving signals from the driving signal generati
Hwang Soo Woong
Lee Hyun Kwan
Park Jin San
Frenel Vanel
Hyundai Electronics Industries Co,. Ltd.
Selitto Behr & Kim
Shalwala Bipin
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