Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2005-12-27
2005-12-27
Awad, Amr A. (Department: 2675)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S204000
Reexamination Certificate
active
06980192
ABSTRACT:
An integrated circuit including a liquid crystal display has a multi-port data output section from which output signals are arranged with respect to a data input signal. Points of changing the signals with respect to a time base are set with time delays that lag behind one another during one period of a reference internal clock signal to reduce the number of simultaneous changes of output signals. The electromagnetic field noise is reduced by a LCD driver when display data are transferred from a LCD timing controller to a source drive IC. The driver includes TFT drive and display timing control circuits that transfer red, green and blue color display data formed of plural bits to the TFT drive circuit for each bit unit formed of plural bits, optionally selected from each of the color display data. A delay unit in the display timing control circuit delays the transfer timing among bit units. A dedicated IC supplies image data to a source driver IC that drives a display section. A detector-comparator circuit detects a coincidence of polarity by comparing a polarity for each bit of red, green and blue of the image data from the dedicated IC. A control circuit outputs color data to the signal line when the coincidence of polarity has been detected. A control circuit outputs the color data that is restored from other data to the source driver IC when the coincidence of polarity of bit has been detected.
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Aoki Kazuo
Gondo Kenji
Matsumura Tatsuya
Awad Amr A.
Kabushiki Kaisha Advanced Display
McDermott Will & Emery LLP
Nelson Alecia D.
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