Liquid crystal cells – elements and systems – Particular excitation of liquid crystal – Electrical excitation of liquid crystal
Reexamination Certificate
2002-12-26
2004-10-05
Kim, Robert H. (Department: 2871)
Liquid crystal cells, elements and systems
Particular excitation of liquid crystal
Electrical excitation of liquid crystal
C349S054000, C349S139000
Reexamination Certificate
active
06801265
ABSTRACT:
This application claims priority of Korean Patent Application No. 87415/2001 filed Dec. 28, 2001, under 35 U.S.C. §119, which is herein fully incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to an active matrix liquid crystal display device having an active panel on which a thin film transistor (TFT) and a pixel electrode connected to the TFT are arranged in a matrix. Especially, the invention relates to a high resolution liquid crystal display device having a shorting bar for testing a thin film transistor.
2. Description of the Background Art
Thin film type flat display devices are under intensive development thanks to their ergonomic advantages of being easily used at any location. Especially, liquid crystal display devices have high resolution and reaction speeds sufficiently fast to realize a mobile image.
Liquid crystal display devices are based on the exploitation of optical anisotropy and polarizability of liquid crystals. That is, by artificially controlling an orientation direction of liquid crystal molecules which has a direction by using their dielectric anisotropy, light can be transmitted or blocked by the optical anisotropy according to the orientation direction. This phenomenon is applied for use in a screen display device.
Currently, an active matrix liquid crystal display device, in which a thin film transistor and a pixel electrode connected thereto are arranged in a matrix form, has wide use thanks to its excellent picture quality.
The structure of a conventional liquid crystal display device will now be described.
One panel (or a color filter panel) of the liquid crystal display device has a structure that red, blue and green color filters are sequentially disposed at the position of pixels on a transparent substrate. A black matrix is formed in mesh form between the color filters. A common electrode is formed on the color filter.
The other panel of the liquid crystal display device has a structure such that pixel electrodes are arranged at portions of pixels designed in matrix form on a transparent substrate.
Signal lines are formed in a horizontal direction of the pixel electrodes, and data lines are formed in a vertical direction of the pixel electrodes.
A thin film transistor is formed at a corner of the pixel electrode to drive the pixel electrode. A gate electrode of the thin film transistor is connected to the signal line (thus, it is also called a gate line), and a source electrode of the thin film transistor is connected to the data line (thus, it is also called a source line).
A pad part is formed at an end of each line to connect the line to an external driving circuit.
The two panels are attached facing one another with a specified space therebetween (the space is called a cell gap), in which liquid crystal material is filled.
In fabricating the active panel of the liquid crystal display device, a method of forming the shorting bar for testing the driving state of each element simultaneously in the process of fabricating the elements will now be described.
FIG. 1
shows a conventional plane structure of one part of the active substrate.
FIGS. 2A through 2E
show conventional sequential section structures in fabricating the active substrate taken along line II—II of FIG.
1
.
FIGS. 3A through 3E
show conventional sequential section structures in fabricating the active substrate taken along line III—III of FIG.
1
.
FIGS. 4A through 4E
show conventional sequential section structures in fabricating the active substrate taken along line IV—IV of FIG.
1
.
As shown in
FIGS. 1
,
2
A,
3
A and
4
A, aluminum or aluminum alloy is deposited on a transparent substrate
1
and patterned to form a gate electrode
11
, a gate line
13
, a gate pad
15
, a source pad
25
and a shorting bar
45
.
The gate lines
13
are isolatedly arranged in line, and the gate electrode
11
is formed by being extended from a certain position of the gate line
13
. The gate pad
15
is formed at an end of the gate line
13
, and the source pad
25
is formed at an end of the source line
23
(to be formed later). The shorting bar
45
is formed at an outer circumference of the substrate
1
and connects the gate pad
15
and the source
25
.
In general, a hillock can easily grow on the surface of a metal layer containing aluminum, thereby causing trouble when other materials are afterwards stacked on the metal layer.
Thus, in order to prevent a hillock from forming, the metal layer is anodized to form an anodized film
19
. At this time, since the gate electrode
11
, the gate line
13
, the gate pad
15
and the source pad
25
are connected to each other through the shorting bar
45
, it is suitable for anodic oxidation.
In this respect, however, current can scarcely penetrate the anodized surface. Thus, anodic oxidation is preferably not performed on the gate pad
15
to be connected to an external terminal and the source pad
25
. For this, a film is formed on the gate pad
15
and the source pad
25
by using a photoresist to prevent anodic oxidation, and then the anodic oxidation process is performed.
As a result, at the thin film transistor part, as shown in
FIG. 2A
, the gate electrode
11
including the anodized film is formed at the surface of the substrate
1
.
Also, at the part where the gate pad
15
and the shorting bar
45
are formed, as shown in
FIG. 3A
, the shorting bar
45
and the gate line
13
including the anodized film
19
are formed at the surface of the substrate
1
, and the gate pad
15
is formed at the surface of the substrate
1
, including no anodized film
19
.
At the part where the source pad
25
and the shorting bar
45
are formed, as shown in
FIG. 4A
, the shorting bar
45
including the anodized film
19
is formed at the surface of the substrate
1
, and the source pad
25
is formed at the surface of the substrate
1
, such that the source pad
25
includes no anodized film
19
.
With reference to
FIGS. 2B
,
3
B and
4
B, silicon oxide or silicon nitride is deposited at the entire surface of the substrate
1
with the gate electrode
11
, the gate line
13
, the gate pad
15
, the source pad
25
and the shorting bar
45
formed thereon, so as to form a gate insulation film
17
.
FIG. 2B
shows an intrinsic semiconductor material and a doped semiconductor material containing an impurity are formed in succession on the gate insulation film
17
, and then patterned by using photolithography to form a semiconductor layer
35
and an impurity semiconductor layer
37
at that part of the thin film transistor.
And then, as shown in
FIGS. 3B and 4B
, the gate insulation film
17
at the part covering the gate pad
15
and the source pad
25
is etched to form first gate contact holes
51
and first source contact holes
61
.
The first gate contact holes
51
expose the non-anodized portion of the gate pad
15
. The first source contact holes
61
expose the non-anodized portion of the source pad
26
.
With reference to
FIGS. 2C
,
3
C and
4
C, a metal such as chromium is deposited on the entire surface of the substrate with the semiconductor layer
35
and the impurity semiconductor layer
37
formed thereon. Then, patterning forms a source electrode
21
, a drain electrode
31
, a source line
23
, a gate pad intermediate electrode
55
and a source pad intermediate electrode
65
.
Accordingly, at the part where the thin film transistor is formed, as shown in
FIG. 2C
, the source electrode
21
and the drain electrode
31
are patterned to face each other over the gate electrode
11
. The impurity semiconductor layer
37
exposed through the source electrode
21
and the drain electrode
31
is etched so that the source electrode
21
and the drain electrode
31
can be electrically isolated.
At the part where the gate pad
15
is formed, as shown in
FIG. 3C
, the gate pad intermediate electrode
55
is connected to the gate pad
15
through the first gate contact holes
51
formed at the gate insulation film
17
.
At the part where the source pad
25
is formed, as
Choi Seung-Kyu
Kim Hyun-Tae
Birch & Stewart Kolasch & Birch, LLP
Kim Robert H.
LG. Phillips LCD Co., Ltd.
Qi Mike
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