Liquid crystal cells – elements and systems – Particular excitation of liquid crystal – Electrical excitation of liquid crystal
Reexamination Certificate
1999-08-23
2001-08-28
Dudek, James A. (Department: 2871)
Liquid crystal cells, elements and systems
Particular excitation of liquid crystal
Electrical excitation of liquid crystal
C349S141000
Reexamination Certificate
active
06281953
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a liquid crystal display and a method of manufacturing the same, more particularly to a liquid crystal display having high aperture ratio and high transmittance, which is driven by a fringe field.
DESCRIPTION OF RELATED ART
The liquid crystal display having high aperture ratio and high transmittance which is switched by the fringe field, has been proposed to improve those characteristics of low transmittance and low aperture ratio in an IPS liquid crystal display which is switched by an in-plane field parallel with substrates.
The liquid crystal display having high aperture ratio and high transmittance has a counter electrode and a pixel electrode, both made of a transparent conductor, and a distance between those electrodes is formed narrower than a distance between upper and lower substrates thereby forming a fringe field over the counter electrode and the pixel electrode.
FIG. 1
is a cross-sectional view showing a general liquid crystal display having high aperture ratio and high transmittance.
Referring to
FIG. 1
, an opaque metal layer for gate bus line, for example an Al-contained alloy layer or a deposition layer containing Al layer is formed on a transparent lower substrate
10
so as to reduce signal delay. A predetermined portion of the opaque metal layer for gate bus line
11
is patterned, thereby forming a gate bus line
11
and a common signal line(not shown). A transparent conductive layer, for example an ITO(indium tin oxide) is deposited over the lower substrate
10
in which the gate bus line
11
and the common signal line are formed. And then, a predetermined portion of the transparent conductive layer is patterned to be contacted with the common signal line, thereby forming a counter electrode
12
having a rectangular plate shape. A gate insulating layer
13
is formed over the lower substrate
10
in which the gate bus line
11
and the counter electrode
12
are formed. An amorphous silicon layer
14
is deposited over the gate insulating layer
13
so as to overlap with a selected portion of the gate bus line
11
. An etch stopper
15
is formed over the amorphous silicon layer
14
to correspond with a predetermined portion of the gate bus line
11
. An impurity-doped amorphous silicon layer
16
is deposited over the amorphous silicon layer
14
. Predetermined portions of the amorphous silicon layer
14
and the impurity-doped amorphous silicon layer
16
are patterned, thereby forming a channel layer and an ohmic layer. A metal layer for data bus line, for example an Mo/Al/Mo layer is deposited over the gate insulating layer
13
and the metal layer is patterned to be remained at both sides of the channel layer, thereby forming source and drain electrodes
17
a
,
17
b
. Accordingly, a thin film transistor is completed.
A transparent conductive layer is deposited over the gate insulating layer
13
in which the source and the drain electrodes
17
a
,
17
b
are formed. A predetermined portion of the transparent conductive layer is patterned to overlap with the counter electrode
12
, thereby forming a pixel electrode
18
. At this time, the pixel electrode
18
is formed in the shape of a comb so that the pixel electrode
18
makes a fringe field together with the counter electrode
12
. To protect the thin film transistor and the pixel electrode
18
, a passivation layer
19
is formed on the gate insulating layer
13
.
A transparent upper substrate
100
is opposed to the lower substrate
10
by a selected distance. A black matrix
101
is formed at an inner side of the upper substrate
100
so as to correspond to the thin film transistor, and a color filter
102
is formed at one side of the black matrix so as to correspond to the pixel electrode
18
. A first alignment layer
104
a
is formed on surfaces of the black matrix
101
and the color filter
102
. A second alignment layer
104
b
is formed on a surface of the passivation layer
19
. A liquid crystal layer
105
is sandwiched at a space between the upper substrate
100
and the lower substrate
10
.
However, the conventional liquid crystal display having high aperture ratio and high transmittance incurs following problems.
The Al-contained alloy layer for consisting the gate bus line and the ITO material consisting the counter electrode have similar etching selectivity. Therefore, when the counter electrode is formed, the gate bus line and the common signal line may be lost or damaged by an ITO etchant. When the gate bus line is lost, thus resistance of the gate line is increased and also the signal delay time is increased. To solve foregoing problems, an MoW material which does not react to the ITO etchant has been used for the gate bus line. However, this MoW material has higher resistance than the Al-contained alloy layer, the signal delay is still occurred.
Furthermore, the fringe field E formed between the counter electrode
12
and the pixel electrode
18
, drives liquid crystal molecules of the liquid crystal layer. At this time, a path that the substantial fringe field is formed, is as follows; the passivation layer
19
, the second alignment layer
104
b
, the liquid crystal layer
105
, the second alignment layer
104
b
and the gate insulating layer
13
. Like this, since there is formed a multi-layered insulating layer in the spaces where the fringe field is formed, intensity of the fringe field is very low. Accordingly, a relatively high voltage is required to obtain a predetermined degree of the fringe field intensity, and an afterimage may be shown.
SUMMARY OF THE INVENTION
Therefore, it is one object of the present invention to provide a liquid crystal display having high aperture ratio and high transmittance, and also capable of preventing the signal delay in a gate bus line.
Further, it is another object of the present invention to provide a liquid crystal display having high aperture ratio and high transmittance, and also capable of improving the intensity of fringe field without requiring high voltage.
It is still an object of the present invention to provide a method of manufacturing the liquid crystal display having high aperture ratio and high transmittance.
To accomplish foregoing objects of the present invention, the method of manufacturing the liquid crystal display includes the steps of: forming a gate bus line and a common signal line on a lower substrate; forming a gate insulating layer on the lower substrate in which the gate bus line and the common signal line are formed; forming a channel layer on a selected portion of the gate insulating layer comprising the gate bus line; forming a source and a drain electrodes so as to overlap with both sides of the channel layer, and a data bus line being arranged perpendicular to the gate bus line; etching the gate insulating layer so as to expose a selected portion of the common signal line; forming a counter electrode by depositing an ITO layer on the gate insulating layer, and by patterning a selected portion thereof so as to contact with the exposed common signal line; depositing a passivation layer over the gate insulating layer in which the counter electrode is formed; etching the passivation layer so as to expose a selected portion of the drain electrode; and forming a pixel electrode, by depositing the ITO layer on the passivation layer so as to contact to the exposed drain electrode, and by patterning a selected portion of the ITO layer so that a fringe field is formed by being overlapped with the counter electrode.
In another aspect of the present invention, the liquid crystal display includes: a gate bus line and a common signal line, both disposed on a surface of a lower substrate; a gate insulating layer coated over the lower substrate in which the gate bus line and the common signal line are formed; a thin film transistor formed on a selected portion of the gate bus line; a counter electrode contacted with the common signal line, disposed at a selected portion on the gate insulating layer and made of an ITO material; a passivation layer formed on th
Lee Seok Lyul
Lee Seung Hee
Park In Cheol
Dudek James A.
Hyundai Electronics Industries Co,. Ltd.
Ladas & Parry
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