Computer graphics processing and selective visual display system – Display driving control circuitry – Display power source
Reexamination Certificate
2001-12-12
2004-01-20
Mengistu, Amare (Department: 2673)
Computer graphics processing and selective visual display system
Display driving control circuitry
Display power source
C341S144000, C348S674000
Reexamination Certificate
active
06680733
ABSTRACT:
The present invention claims the benefit of Korean Patent Application No. P2000-76848 filed in Korea on Dec. 15, 2000, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is generally related to a liquid crystal display (LCD), and more particularly to a liquid crystal display with a gamma voltage controller for finely aligning the output of a programmable digital-to-analog converter by precisely controlling the voltage difference between each level of the output.
2. Discussion of the Related Art
A liquid crystal display (LCD) with active matrix driving system utilizes thin film transistors (TFT) as switching elements to display natural-like moving pictures. Currently available LCD devices consume less power, emit significantly less harmful electromagnetic waves, save more work space due to their slimness and light weight, and bring more convenience to work environment than conventional cathode ray tube (CRT) devices. Therefore, as a display device, the LCD device replaces the CRT device in various applications, such as, for example, computer monitors, television displays, etc. Recently, with regard to video media, the conventional analog video signal transmission method has being changed to a digital video signal transmission method with which the compression of the information is easier. The digital signal transmission provides the audience with a high resolution picture. Thus, an LCD, which is a kind of a display device, must be capable of being driven by digital video signals instead of the conventional analog video signals.
FIG. 1
illustrates a block diagram of a related art active matrix LCD device. Referring to
FIG. 1
, the architecture of a related art LCD device includes a column driver
3
that supplies the video data received from an outside video card
1
to a liquid crystal panel
6
; a gamma voltage circuit
4
that supplies a reference voltage to the column driver
3
; a low driver
5
that supplies a scanning signal for controlling the switching action of the thin film transistors (TFT) on the liquid crystal panel
6
; and a controller
2
that controls the column driver
3
and the low driver
5
.
Generally, the liquid crystal panel
6
with the resolution of XGA (1024×768 pixels) has 1024×3(RGB)=3072 source lines. Accordingly, in the LCD with the resolution of XGA, eight (8) column drivers
3
with each column driver having an output terminal of 384 channels are utilized (384×8=3072), and four (4) low drivers
5
with each having an output terminal of 200 channels (200×4=800≈768) are utilized.
The video data received from the digital video card
1
(which may be built in the main body of, for example, a computer) is supplied to the column driver
3
through the controller
2
. Alternatively, an analog video signal from a computer may be sent to the LCD after being converted to digital video data through an interface module (not shown) built in the LCD monitor itself.
FIG. 2
is a block diagram that shows circuit details for a column driver
3
shown in FIG.
1
. As shown in
FIG. 2
, first a data latch
41
latches the video data (
10
,
11
,
12
) input received from the outside video card
1
through the controller
2
. The data latch
41
latches the even and odd numbered video data being inputted by the controller
2
for the LCD panel
6
. A shift register
40
is synchronized with an external clock signal CLK to sequentially generate a latch enable signal for storing the video data into a line latch
42
. The line latch
42
sequentially stores the video data in synchronization with the latch enable signal. The line latch
42
includes a first and a second registers (not shown), each of which has the size of at least one line (here, eight bits). Here, the number of 8-bit source lines connected to one column driver is 384. The line latch
42
moves one line portion of the video data from the first register into the second register soon after that line portion of the video data is stored into the first register. The line latch
42
continues sequential storage of subsequent lines of video data into the first and the second registers.
A plurality of reference voltage signals are applied from the gamma voltage circuit
4
(
FIG. 1
) to a digital-to-analog converter
43
(FIG.
2
), which then selects at least one or two reference voltage signals from the plurality of reference voltage signals in correspondence with each video data being supplied from the second register of the line latch
42
. The digital-to-analog converter
43
also divides each reference voltage signal and outputs the divided reference voltage signal (corresponding to the video data) through an output buffer
44
to each of the source lines as an analog video signal.
The digital-to-analog converter
43
, described herein as an example, has a resistance network distributing the selected reference voltage signal to inner gray level voltages in correspondence with the video data. The reference voltage signal can be controlled externally and is referred to as a tap point voltage. The inner gray level voltage between each tap point is automatically determined by the resistance network inside the digital-to-analog converter
43
. Generally, LCD developers can set the gamma tap voltage, the transmission rate of which is in accordance with the T-V (transmittance-voltage) curve of the LCD panel
6
, on the basis of the information for the driving circuit specification for the resistance network.
FIG. 3
is a graph showing a predetermined relationship of a set of gamma tap voltages GMA
1
-GMA
16
and the transmittance-voltage (T-V) characteristics curve of an LCD panel (e.g., the LCD panel
6
). The setting of the gamma tap voltages is referred to as a Gamma Tuning. It is noted that the L
00
(black) voltage and the L
63
(white) voltage should be set carefully because those voltages decide a contrast ratio for the LCD panel
6
.
FIG. 4
is a block diagram illustration of a related art gamma voltage circuit
4
of
FIG. 1
that utilizes a conventional programmable digital-to-analog converter (DAC). The gamma voltage circuit
4
of related art utilizes as it is (i.e., without any further processing) the gamma voltages being output as reference voltage signals from the programmable DAC. In the case of a programmable digital-to-analog gamma voltage circuit
4
that can be controlled by a 6 bit control signal, a maximum of 64 (2
6
=64) reference voltage signals can be generated. Normally, sixteen (16) out of these sixty-four (64) reference voltage signals (denoted as GMA
1
-GMA
16
) are selected as outputs. Thus, if the VAA voltage is 10V and the programmable DAC is 6-bit, then the controllable voltage step is of 10/64=0.156V. In other words, the programmable digital-to-analog gamma voltage circuit
4
outputs 64 reference voltage signals having a uniform gap of 0.156V. Because the related art programmable digital-to-analog gamma voltage circuit
4
generates the reference voltage signals with a fixed uniform gap, the precise control of the gamma voltages according to the characteristics of the LCD panel
6
becomes impossible.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a liquid crystal display device with a gamma voltage controller that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a liquid crystal display device with a gamma voltage controller that is capable of finely aligning the output of a programmable digital-to-analog converter in a gamma voltage circuit by precisely controlling the voltage difference between each level of the output.
To achieve the objects of the present invention, a gamma voltage circuit for a liquid crystal display according to one embodiment of the present invention includes a programmable digital-to-analog converter (DAC) having a predetermined number of first set of outputs, wherein the programmable DAC is c
Kang Youn Su
Kim Sang Gyu
Woo You Tack
LG. Philips LCD Co. Ltd.
Mengistu Amare
Morgan & Lewis & Bockius, LLP
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