Liquid crystal cells – elements and systems – Particular excitation of liquid crystal – Electrical excitation of liquid crystal
Reexamination Certificate
2000-06-27
2002-12-10
Ton, Toan (Department: 2871)
Liquid crystal cells, elements and systems
Particular excitation of liquid crystal
Electrical excitation of liquid crystal
Reexamination Certificate
active
06493046
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a liquid crystal display device and a fabrication method for the liquid crystal display device, and more particularly, it relates to an active matrix type liquid crystal display device including thin film transistors and a fabrication method for the same.
Recently, an active matrix type liquid crystal display device is widely used as a display device for a personal computer, a thin television set, a display for a video imaging device or a digital camera, or the like. An equivalent circuit of one pixel of an active matrix type liquid crystal display device including a thin film transistor as an active element (hereinafter referred to as the “TFT type liquid crystal display device”) is shown in FIG.
6
. An area where pixels (pixel regions) are arranged in the form of a matrix corresponds to a display region.
In the TFT type liquid crystal display device, each pixel includes a thin film transistor (hereinafter referred to as the “TFT”), and a liquid crystal capacitor C
LC
and a storage capacitor C
S
connected to the drain D of the TFT. The liquid crystal capacitor C
LC
and the storage capacitor C
S
are together designated as a pixel capacitor C
pix
. To the gate G of the TFT, a gate line (scanning line) is connected, and to the source S thereof, a source line (signal line) is connected. During a period when a scan signal is applied to the gate G (i.e., during one scan period), a signal voltage applied from the source line to the source S of the TFT is applied to a drain side electrode of the liquid crystal capacitor C
LC
(hereinafter referred to as the “pixel electrode”) and a drain side electrode of the storage capacitor C
S
(hereinafter referred to as the “storage capacitor electrode”). On the other hand, to another electrode of the liquid crystal capacitor C
LC
(hereinafter referred to as the “counter electrode”) and another electrode of the storage capacitor C
S
(hereinafter referred to as the “storage capacitor counter electrode”), a predetermined counter voltage (common voltage) is applied through a counter electrode or storage capacitor counter electrode line (common line) COM. The storage capacitor counter electrode line COM formed on a TFT substrate is electrically connected to a counter electrode formed on a counter substrate. A net voltage applied to the liquid crystal capacitor C
LC
corresponds to a difference between the signal voltage and the counter voltage. The alignment of liquid crystal is changed in accordance with this voltage, so as to obtain a display state corresponding to the signal voltage.
In a period when a scan signal is not applied to the gate G (namely, when a TFT connected to another gate line is selected), the liquid crystal capacitor C
LC
and the storage capacitor C
S
are electrically insulated from the source line by the TFT. Until the TFT of interest is selected next, the liquid crystal capacitor C
LC
and the storage capacitor C
S
keep the predetermined display state by keeping the previously applied voltage. When the voltage holding property of the TFT and the pixel capacitor C
pix
is low during this period, the display quality is degraded.
In order to attain a desired voltage holding property, a storage capacitor C
S
having a comparatively large capacitance value is sometimes required. When the areas of the storage capacitor electrode and the storage capacitor counter electrode are increased in order to increase the capacity of the storage capacitor C
S
, the aperture ratio can be degraded in a transmission type liquid crystal display device because these electrodes are generally formed from opaque materials.
Japanese Laid-Open Patent Publication No. 5-61071 discloses a TFT type liquid crystal display device using a storage capacitor having large capacity in a pixel.
FIGS. 7A through 7C
are cross-sectional views for showing procedures for forming a TFT and the storage capacitor of the liquid crystal display device described in this publication.
According to the publication, a groove (trench)
122
is formed in the surface of an insulating substrate
121
on which a TFT is to be formed, and the storage capacitor (capacity component) is formed in this groove
122
. Furthermore, the storage capacitor is formed from a first electrode
123
formed integrally with a semiconductor layer of the TFT in the same procedure, a second electrode
126
a
formed from the same material as a gate electrode of the TFT and insulating films
124
a
and
125
a
formed from the same material as a gate insulating layer of the TFT. Thus, the structure and the fabrication process are simplified.
The TFT substrate including the TFT and the storage capacitor part shown in
FIGS. 7A through 7C
are fabricated as follows:
(1) A groove
122
is formed in the surface of a quartz substrate
121
through wet etching using a mixture of HF and NH
4
F (1:6) as an etchant.
(2) A first polysilicon layer
123
with a thickness of 80 nm is formed by the low pressure CVD. Silicon is implanted into the first polysilicon layer
123
twice at energy of 30 keV and dose of 1×10
15
/cm
2
and at energy of 50 keV and dose of 1×10
15
/cm
2
, respectively. The resultant is subjected to solid phase annealing, and part of the first polysilicon layer
123
is removed by etching.
(3) The first polysilicon layer
123
is thermally oxidized at 1000° C., thereby forming a SiO
2
film
124
with a thickness of 50 nm in the surface thereof. A part of the first polysilicon layer
123
not oxidized is ultimately formed into a first electrode of the storage capacitor and the semiconductor layer (the source, the channel and the drain) of the TFT.
(4) With an area of the SiO
2
film
124
where the TFT is to be formed protected by a resist layer, arsenic ions (As
+
) are implanted at energy of 30 kev and dose of 5×10
15
/cm
2
into the part of the first polysilicon layer
123
to be formed into the first electrode of the storage capacitor.
(5) After removing the resist layer, a SiN film
125
with a thickness of 30 nm is formed by the low pressure CVD so as to cover the SiO
2
film
124
.
(6) A second polysilicon layer
126
with a thickness of 350 nm is formed on the entire surface of the substrate by the low pressure CVD, and the resistance is reduced by PSG.
(7) The second polysilicon layer
126
and the SiN film
125
are patterned by using a gas including CF
4
and O
2
(95:5), thereby forming a gate electrode
126
b
of the TFT, a second electrode
126
a
of the storage capacitor, a SiN gate insulating layer
125
b
and a storage capacitor SiN film
125
a.
Then, arsenic ions are implanted through the SiO
2
film
124
into the first polysilicon layer
123
included in the TFT at energy of 160 keV and dose of 1×10
15
/cm
2
, thereby forming an LDD (lightly doped drain).
(8) A resist is formed so as to cover the second electrode
126
b,
and arsenic ions are implanted at energy of 140 keV and dose of 2×10
15
/cm
2
, thereby forming an n-channel. After removing the resist, another resist is formed on the entire surface, and boron ions (B
+
) are implanted at energy of 30 keV and dose of 2×10
15
/cm
2
, thereby forming a p-channel.
(9) After removing the resist, an interlayer insulating film
131
of phosphorus silica glass (PSG) is formed by the low pressure CVD.
(10) A first contact hole
132
is formed in the interlayer insulating film
131
and the SiO
2
film
124
by the wet etching using the mixture of HF and NH
4
F.
(11) An ITO (indium tin oxide) film
129
with a thickness of 140 nm is formed by sputtering at 400° C. The ITO film
129
is wet etched by using an etchant including HCl, H
2
O and HNO
3
(300:300:50), thereby patterning the ITO film
129
. Then, by using a resist as a mask, a second contact hole
134
is formed in the ITO film
129
by the wet etching using the mixture of HF and NH
4
F.
(12) An AlSi layer with a thickness of 600 nm is deposited by sputtering on the entire surface, and the AlSi layer is patterned into an electrode
130
by the wet etching usin
Nixon & Vanderhye P.C.
Rude Timothy L
Sharp Kabushiki Kaisha
Ton Toan
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