Liquid crystal cells – elements and systems – Particular structure – Having significant detail of cell structure only
Reexamination Certificate
2001-10-04
2003-03-04
Dudek, James (Department: 2871)
Liquid crystal cells, elements and systems
Particular structure
Having significant detail of cell structure only
C349S043000
Reexamination Certificate
active
06529258
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device and, more specifically, to such an LCD device as having an upper-level pattern such as a wiring layer crossing a lower-level pattern such as a semiconductor layer.
2. Description of the Related Art
While an LCD device is classified roughly into an active type and a passive type, the active type LCD device has been recently widely employed. In the active type, an active element such as a transistor and a metal-insulator-metal (M IM) element is used as a switching element for driving an liquid crystal cell. As such a transistor, a thin film transistor (TFT) of the inverted staggered type is usually used.
The TFT of the inverted staggered type includes basically a gate electrode formed on a substrate such as glass, a semiconductor layer formed on a gate insulating film covering the gate electrode, and source and drain electrodes which are in an ohmic contact with the semiconductor layer. The source (drain) electrode is connected to a signal line to which image data is supplied, and a drain (source) electrode is connected to a pixel electrode of a pixel (picture element). The gate electrode is connected to a scan line to which a scan signal is supplied to render the TFT conductive and non-conductive.
As another TFT, a staggered type is known in which a semiconductor layer and source/drain electrodes are formed in lower level than a gate insulating film, and a gate electrode is formed on the gate insulating layer.
In case of performing a display in X and Y axes plane, the liquid crystal pixels and thus the switching transistors are arranged in a matrix. Therefore, a plurality of scan lines are formed in parallel to each other in the X direction, and a plurality of signal lines are formed in parallel to each other in the Y direction, each TFT being thus disposed on the different one of the intersections of the scan and signal lines. As a result, the scan and signal lines cross to each other with an electrical isolation between the scan and signal lines. In the LCD device employing the inverted staggered type, the scan and signal lines are formed respectively as a lower-level wiring layer and an upper-level wiring layer. In the staggered type, on the other hand, the scan and signal lines are formed respectively as an upper-level wiring layer and a lower-level wiring layer. The electrical isolation between the scan and signal lines is attained by utilizing the gate insulating layer, as is apparent from the above. In order to avoid the short-circuit between the crossing lines that may occur due to pinhole(s) formed in the gate insulating layer, an island semiconductor layer, which is patterned simultaneously with forming the semiconductor layer functioning as the channel region of the TFT, intervenes between the scan and signal lines.
Thus, the upper-level wiring layer crosses the edge of the lower-level pattern such as the island semiconductor layer. The upper-level wiring layer is formed by depositing a wiring material over the entire surface of the substrate and then patterning the wiring material by selective-etching process using the photolithography. At this time, due to the lowering in adhesive strength of the wiring material to the lower-level pattern that are caused by the step at the edge of the lower-level pattern, the etchant used in the selective-etching process soaks between the lower-level pattern and the wiring material along the edge of the lower-level pattern to remove desired portions of the wiring material. At the worst case, the upper-level wiring layer is broken down. Such phenomena may takes place at the crossing portions of the source/drain electrodes and the semiconductor channel layer of the TFT.
In order to solve the above problems, therefore, the Japanese Laid-Open (Kokai) Patent Publication Hei 2-20830 discloses providing, in a plane view, at least one protrusion and/or indentation at the edge of the crossing portion of the lower-level pattern to the upper-level portion. This countermeasure is to make large the effective length of the crossing edge of the lower-level pattern to the upper-level pattern by the protrusion and/or indentation. With such construction, even if the etchant soaks between the upper-level and lower-level pattern, the breaking-down of the upper-level pattern is prevented.
More specifically, as the partial plane view of the LCD device according to the above publication is shown in
FIG. 5
, this device employs the TFT
1
of the inverted staggered type. This TFT
1
thus includes scan wiring layer
2
, an intrinsic amorphous silicon (a-Si) layer
3
a
as a semiconductor layer that is formed on a gate insulating layer covering the scan line
2
, a protective layer
3
b
formed thereover to protect the channel region of the a-Si layer
3
, n+ (high-conductivity) amorphous silicon (n-a-Si) layers
3
c
formed on the a-Si layer
3
to present an ohmic contact with electrodes, source and drain electrodes
4
a
and
4
b
formed on the n-a-Si layers
3
c
, and an pixel (picture element) electrode
5
connected to the electrode
4
b
. In this device, apart of the scan line also functions as agate electrode, and the electrode
4
a
is branched from a signal line
4
. At the crossing portion of the scan and signal lines
2
and
4
, for the reasons described above, there are provided in addition to the gate insulating film, an island a-Si layer
3
a
, an island n-a-Si layer
3
c
and a channel protective layer
3
b.
In order to prevent the breaking-down of the signal line
4
(the upper pattern), each of the a-Si layers
3
a
and
3
c
is patterned such that its edge, over which the signal line
4
or the electrodes
4
a
and
4
b
cross, becomes concavo-convex in plane view by providing two protrusions. By this patterning, the length of the crossing edge line of each a-Si layer
3
to the wiring line
4
or the electrodes
4
a
and
4
b
is made larger. As a result, even if the etchant for selectively patterning the wiring line
4
and the electrodes
4
a
and
4
b
soaks along the such crossing edge line, the braking-down of the line
4
and the electrodes
4
a
and
4
b
is prevented.
The LCD display is requested not only solving the problems in its manufacturing process but also enhancing its display quality. One of the issues to be enhanced in the display quality is the so-called aperture ratio. That is, it is requested to increase the aperture ratio. This request is achieved by make the areas of the light impermissible layers as small as possible. To this end, in the LCD device shown in
FIG. 5
, the wiring layer such as the signal line
4
and the scan line
2
is required to be made small in its width to thereby increase the area of the pixel electrode
5
surrounded by these wiring layers
4
and
2
.
It has been, however, recognized by the inventors that the following serious problems caused by lowering the width of the signal line
4
(upper wiring layer) of the LCD device shown in
FIG. 5
for the purpose of increasing the aperture ratio. Specifically, the signal line
4
is patterned by the selective-etching method performed on the wiring material layer formed over the entire surface of the substrate, and to do the selective-etching, it is required to form a mask layer on the wiring material. The mask layer is usually formed by projecting a wiring pattern, which is provided on a photo-mask, on a photoresist layer formed on the wiring material layer. At this time, it is unavoidable that the deviation in alignment between the photo-mask and the LCD substrate occurs. As a result, the signal line
4
is not formed in the designed center location, but is actually formed with some deviation in the up-and-down and/or left-and right direction from the designed center location. For this reason, if the width of the signal line
4
is made small for the high aperture ratio, such a case may occur that one of the side edges defining the width of the signal line
4
(in FIG.
5
, the side edge of the line
4
in the Y
Tamura Fuminori
Watanabe Makoto
Choate Hall & Stewart
Dudek James
NEC Corporation
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