Liquid crystal display device having redundant pairs of address

Details Liquid crystal display device having redundant pairs of address Liquid crystal display device having redundant pairs of address

1980-12-16

1983-01-11

Martin, John C.

Static information storage and retrieval

Interconnection arrangements

365149, 365189, 365231, 358236, 340784, 29575, G11C 506, G11C 802, G11C 1124, H04N 574

Patent

active

043685234

ABSTRACT:
Disclosed is a memory device having a plurality of memory cells arranged in a matrix form; address buses connected to the memory cells and forming respective rows of the matrix; and data buses connected to the memory cells and forming respective columns of the matrix.
The address buses or the data buses are formed by paired bus lines, and bridge lines are formed between one and the other of the paired bus lines.

REFERENCES:
Schuster, "Multiple Word/Bit Line Redundancy for Semiconductor Memories", IEEE Journal of Solid-State Circuits, vol. SC-13, No. 5, Oct. 1978, pp. 698-703.
Electronics Science 79-84 (Jun. 1979).

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