Computer graphics processing and selective visual display system – Display driving control circuitry
Reexamination Certificate
2000-07-19
2003-08-26
Shalwala, Bipin (Department: 2673)
Computer graphics processing and selective visual display system
Display driving control circuitry
C345S001100, C345S030000, C345S042000, C345S055000, C345S087000, C345S090000, C345S099000, C345S100000, C345S103000
Reexamination Certificate
active
06611261
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to liquid-crystal-display devices, and particularly relates to a liquid-crystal-display device that is of a type having peripheral circuits integrated therein, and is capable of displaying a large and fine screen.
2. Description of the Related Art
In recent years, there has been a demand for a large-scale fine display as well as for a small-scale fine display. Such a demand has led to an increase in popularity of liquid-crystal-display devices using p-SiTFTs (poly-silicon thin film transistors), which allows the liquid-crystal display unit and peripheral circuits to be formed as an integrated device.
One type of liquid-crystal-display devices, which is relevant to the present invention, has a liquid-crystal-display area thereof divided into a plurality of blocks, and a video signal is written into the blocks one block after another. Hereinafter, such a driving method is referred to as a simple-block-succession method.
FIG. 1
is a block diagram of a liquid-crystal-display device
10
which is an example of a liquid-crystal-display device driven by the simple-block-succession method.
As shown in
FIG. 1
, the liquid-crystal-display device
10
includes a digital driver LSI
12
, common-signal lines D
1
through Dn, analog switches
14
, block-control lines BL, a gate driver
16
, and a display matrix
18
. The digital driver LSI
12
, the common-signal lines D
1
through Dn, the analog switches
14
, etc., together form a data driver
19
.
The display matrix
18
is divided into N blocks B
1
through BN, and each block is provided with scan lines
20
and signal lines
22
arranged in a matrix form. At intersections of the scan lines
20
and the signal lines
22
are situated pixel cells
24
.
The analog switches
14
include as many as n switches provided for each of the blocks B
1
through BN. The analog switches
14
are connected to the common-signal lines D
1
through Dn via lead lines
31
. Each of the analog switches
14
is also connected to the block-control lines BL. The analog switches
14
are turned on when block-control signals BL
1
through BLN are supplied through the block-control lines BL.
The digital driver LSI
12
receives digital signals from an external data-supply device (not shown), and generates video signals Vs based on the received digital signal. The digital driver LSI
12
supplies the video signals Vs to each of the blocks B
1
through BN via the common-signal lines D
1
through Dn on a time-division basis.
When the liquid-crystal-display device
10
operates, a scan signal Vg supplied from the gate driver
16
activates successively the pixel cells
24
one line after another. In the liquid-crystal-display device
10
, a horizontal scan period Th is comprised of N block-control periods Tb. During the first block-control period Tb, the block-control signal BL
1
turns on n analog switches
14
that are connected to the signal lines
22
within the block B
1
. During the second block-control period Tb, the block-control signal BL
2
turns on n analog switches
14
that are connected to the signal lines
22
inside the block B
2
. Further, during the N-th block-control period Tb that is the last in one horizontal scan period Th, n analog switches
14
connected to the signal lines
22
in the block BN are turned on by the block-control-signal BLN. Video signals Vs generated by the digital driver LSI
12
are supplied through the turned-on analog switches
14
to the activated pixel cells
24
, thereby effecting liquid-crystal display.
FIG. 2
is a block diagram for explaining configurations of the data driver
19
and the display matrix
18
provided in the liquid-crystal-display device
10
.
FIG. 2
shows a configuration of n being
384
and N being
10
in the configuration of FIG.
1
. Namely, the display matrix
18
is divided into
10
blocks, and the number of horizontal pixels is 3840 (=384×10).
As shown in
FIG. 2
, the data driver
19
includes the digital driver LSI
12
, the common-signal lines D
1
through D
384
, the analog switches
14
, etc. The digital driver LSI
12
has 384-bit outputs, which correspond to the common-signal lines D
1
through D
384
. The analog switches
14
are provided as many as 384 for each of the blocks B
1
through B
10
. The common-signal lines D
1
through D
384
are connected to a corresponding one of the analog switches
14
in each of the blocks B
1
through B
10
.
In general, one horizontal scan period Th becomes shorter as size of the liquid-crystal-display area increases. In the VGA format having 640×3(RGB)×480 pixels, the horizontal scan period Th is approximately 34.6 &mgr;s whereas in the QXGA format having 2048×3×1536 pixels, the horizontal scan period Th is approximately 10.8 &mgr;s.
In the liquid-crystal-display device
10
described above, a time period required for writing signals in one block, i.e., the block-control period Tb, is determined by
1
horizontal scan period Th/the number of blocks N. As the horizontal scan period Th decreases with an increase in size of the display area, the block-control periods Tb also decreases.
In order to maintain a sufficient block-control periods Tb, width of each block may be widened, and the number N of the blocks may be decreased. When this measure is taken, however, the problem as follows will be encountered.
As shown in
FIG. 1
, the liquid-crystal-display device
10
has a data width (number of bits) of one block being equal to the number n of the common-signal lines D
1
through Dn. When the data width is increased, the number of the common-signal lines is also increased, resulting in an increase in space required for the wiring of the signal lines. This makes larger the frame size of the display panel of the liquid-crystal-display device
10
.
For example, when an XGA panel having 3072 horizontal pixels and a 22-microsecond horizontal scan period Th is implemented by using 8 blocks having the data width of 384 bits, the block-control periods Tb will be longer than 2.0 &mgr;s. In order to achieve a 2.0-microsecond block-control periods Tb by using a QXGA panel having 6144 horizontal pixels and an 11-microsecond horizontal scan period Th, 4 blocks each having a data width of 1536 bits must be used. In this case, assuming that the wiring pitch is 16 &mgr;m, the wiring width of the common-signal lines D
1
to D
384
in the XGA panel is 6.14 mm (16 &mgr;m×384 bits). In contrast, the wiring width of the common-signal lines D
1
to D
1536
of the QXGA panel is 24.6 mm (16 &mgr;m×1536 bits). This is quite a wide width.
Further, when the digital driver LSI
12
is used as an external attachment to the liquid-crystal-display device
10
, an increase in the width of the common-signal lines D
1
through Dn results in an increase in the number of outputs of the digital driver LSI
12
. Consequently, the digital driver LSI
12
becomes highly expensive, and the yield in the manufacturing process decreases.
Moreover, widening the data width leads to an increase in the number of intersections of the common-signal lines D
1
through Dn and the lead lines
31
shown in
FIG. 1
, resulting in the capacitance load on the common-signal lines D
1
through Dn being increased. This means an increased time constant. In the QXGA panel, for example, a single common-signal line may have more than 6144 intersections. In such a case, the capacitance load of one intersection point may be 4 fF, for example, and, then, the total capacitance may be as large as 25 pF.
As shown in
FIG. 1
, the liquid-crystal-display device
10
has the common-signal lines D
1
through Dn the length approximately equal to the width of the display matrix
18
. As the size of the display matrix
18
is increased, therefore, the length of the common-signal lines D
1
through Dn is also increased. The resulting increase in the wiring resistance contributes to a rise in the time constant.
Accordingly, there is a need for a liquid-crystal-display device which ca
Takahara Kazuhiro
Zhang Hong Yong
Fujitsu Display Technologies Corp.
Greer Burns & Crain Ltd.
Kovalick Vincent E.
Shalwala Bipin
LandOfFree
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