Liquid crystal display device having improved aperture ratio

Liquid crystal cells – elements and systems – Particular structure – Having significant detail of cell structure only

Reexamination Certificate

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Details

C349S145000, C349S042000, C257S072000

Reexamination Certificate

active

06486935

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device having a improved aperture ratio.
2. Description of the Related Art
In general, an active matrix type-liquid crystal display (AM-LCD) devices is thin, so that it is often used in various display devices. In this AM-LCD device, one TFT is provided as a switching element for each pixel, so that individual pixel electrodes are independently driven. The contrast is therefore not reduced based upon the reduction of a duty ratio, and also the angle of visibility is not reduced, even when the capacity of display is increased to increase the number of lines.
FIG. 1
shows a plan view of a prior AM-LCD.
Referring to
FIG. 1
, gate lines
11
-
1
and
11
-
1
and data lines
13
-
1
and
13
-
2
are arranged in a matrix on a transparent insulating layer
10
such as a glass. The gate line
11
-
1
and
11
-
2
are arranged in parallel in the direction of x axis. The data lines
13
-
1
and
13
-
2
are arranged in parallel in the direction of a y axis which is substantially perpendicular to the x axis, thereby defining pixel regions
100
. Preferably, the length of the y axis direction of the pixel region
100
is longer than that of the x axis direction. Each the line width GW of the gate lines
11
-
1
and
11
-
2
is 10 to 12 &mgr;m and each the line width DW of the data lines
13
-
1
and
13
-
2
is 7 to 9 &mgr;m. TFTs are disposed respectively at the cross portions of the gate line
11
-
1
and
11
-
2
and the data lines
13
-
1
and
13
-
2
. In
FIG. 1
, one TFT
20
in only showed the cross portion of the gate line
11
-
1
and data line
13
-
1
. The TPT
20
includes a gate
11
a
projected from the gate line
11
-
1
, a drain
13
a
projected from the data line
13
-
1
and overlapped with the portion of the gate
11
a
, and a source
13
b
separated from the drain
13
a
and overlapped with the portion of the gate
11
a
. A pixel electrodes
15
are disposed at the pixel regions
100
except for the TFT
20
to be separated from the gate lines
11
-
1
and
11
-
2
and the data lines
13
-
1
and
13
-
2
, with selected distance and to be in contact with the source
13
b.
In the prior AM-LCD above described, the gate lines
11
-
1
and
11
-
2
are formed of an opaque material such as Al and Cr while the pixel electrode
15
are formed of a transparent material such an ITO (Indium Tin Oxide). An a result, the gate lines
11
-
1
and
11
-
2
and the data lions
13
-
1
and
13
-
2
block off light, thereby reducing aperture ratio.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to a liquid crystal display device which can improve aperture ratio by minimizing light blocking.
To accomplish this above object, a liquid crystal display device according to a first embodiment of the present invention includes: an insulating substrate; a plurality of gate lines formed on the substrate and arranged in parallel in a first direction; a gate insulating layer formed on the substrate where the plurality of gate lines are formed; a plurality of data lines formed on the gate insulating layer and arranged in parallel in the first direction, overlapping with the plurality of gate lines, respectively; a plurality of pixel regions, each first direction length of the pixel regions extending as the line width of the date line, each second direction length of the pixel region being defined by the distance between the gate linen, the second direction being substantially perpendicular to the first direction; a plurality of pixel electrodes disposed on the plurality of pixel regions, respectively; and a plurality of thin film transistors disposed at one side of the plurality of pixel regions, respectively.
Furthermore, a liquid crystal display device according to a second embodiment of the present invention includes: an insulating substrate; a plurality of gate lines formed on the substrate and arranged in parallel in a first direction; a gate insulating layer formed on the substrate where the plurality of gate lines are formed; a plurality of data lines formed on the gate insulating layer and arranged in parallel in the first direction, overlapping with the plurality of gate lines, respectively; a plurality of pixel regions, each first direction length of the pixel regions extending as the line width of the gate lines, each second direction length of the pixel region being defined by the distance between the data lines, the second direction being substantially perpendicular to the first direction; a plurality of pixel electrodes disposed at the plurality of pixel regions, respectively; and a plurality of thin film transistors disposed at one side of the plurality of pixel regions, respectively.
In the first and second embodiments, the thin film transistor includes: a gate protected from the gate line; a drain projected from the data line and overlapped with the gate; and a source separated from the drain and overlapped with the gate, the source being in contact with the pixel electrode. The gate and data lines are formed of an oblique metal layer, respectively and the pixel electrode is formed of a transparent metal layer such as an ITO.
Furthermore, a liquid crystal display device according to a third embodiment of the present invention includes: an insulating substrate; a plurality of gate lines formed on the substrate and arranged in parallel in a first direction; a plurality of data lines arranged in parallel in the first direction, overlapping with the plurality of gate lines, respectively; a plurality of pixel regions, each first direction length of the pixel regions extending an the line width of the data lines, each second direction length of the pixel regions being defined by the distance between the gate lines, the second direction being substantially perpendicular to the first direction; a plurality of pixel electrodes disposed on the plurality of pixel regions, respectively; a plurality of thin film transistors disposed between the plurality of gate lines and the plurality of data lines, respectively; and a gate insulating layer and an intermediate insulating layer interposed between the plurality of gate lines and the plurality of data lines, the intermediate insulating layer having a contact hole.
In the third embodiment, the thin film transistor includes: a gate is formed on the substrate; a channel layer formed on the gate insulating layer over the gate; a drain formed on the channel layer to be overlapped with one side of the gate; and a source formed on the channel layer to be overlapped with the other side of the gate and be in contact with the pixel electrode, wherein, the drain is connected to the data line through the contact hole. The intermediate insulating layer is formed of a material having develop type of PC335, PC403, series material thereof, or BCB (made in DWO company) of a dry etch type, as material having a relative low dielectric constant. The gate and data lines are formed of an oblique metal layer, respectively and the pixel electrode is formed of a transparent metal layer such as an ITO.
Additional object, advantages and novel features of the invention will be not forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.


REFERENCES:
patent: 4955697 (1990-09-01), Tsukada et al.
patent: 5457553 (1995-10-01), Mori
patent: 5535028 (1996-07-01), Bae et al.
patent: 5574582 (1996-11-01), Takeda et al.
patent: 5760854 (1998-06-01), Ono et al.
patent: 5818412 (1998-10-01), Maekawa
patent: 5966189 (1999-10-01), Matsuo
patent: 6236383 (2001-05-01), Nakajima et al.
patent: 5-257162 (1993-10-01), None

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