Liquid crystal cells – elements and systems – Nominal manufacturing methods or post manufacturing... – Sealing of liquid crystal
Reexamination Certificate
2002-08-19
2004-05-04
Ngo, Julie-Huyen L. (Department: 2871)
Liquid crystal cells, elements and systems
Nominal manufacturing methods or post manufacturing...
Sealing of liquid crystal
C349S139000, C349S149000, C349S151000, C349S153000
Reexamination Certificate
active
06731369
ABSTRACT:
This application claims the benefit of Korean Patent Application No. 2001-50165, filed on Aug. 21, 2001, which is hereby incorporated by reference for all purposes as if fully set forth herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly to a driving circuit portion of an LCD device.
2. Discussion of the Related Art
Flat panel display (FPD) devices having small size, lightweight, and low power consumption have been a subject of recent research in the coming of the information age. Among many kinds of FPD devices, LCD devices are widely developed and used because of their excellent characteristics of resolution, color display and display quality.
Generally, LCD devices include an upper substrate and a lower substrate facing each other with liquid crystal molecules interposed therebetween. Each substrate has an electrode on an inner surface thereof. An electric field is generated by applying a voltage to the electrodes, thereby driving the liquid crystal molecules to display images depending on light transmittance.
FIG. 1
is a schematic cross-sectional view of a conventional LCD device.
In
FIG. 1
, a conventional LCD device has a first region “A” where images are displayed, and a second region “B” where pads (not shown) connected to driving circuits to apply a signal to the first region “A” are disposed. At the first region “A”, a gate electrode
11
of conductive material such as metal is formed on a first substrate
10
. A gate insulating layer
12
of silicon nitride (SiNx) or silicon oxide (SiO
2
) is formed on the gate electrode
11
. An active layer
13
of amorphous silicon and an ohmic contact layer
14
of impurity-doped amorphous silicon are sequentially formed on the gate insulating layer
12
over the gate electrode
11
. Source and drain electrodes
15
a
and
15
b
of conductive material such as metal are formed on the ohmic contact layer
14
. The source and drain electrodes
15
a
and
15
b
compose a thin film transistor (TFT) “T” with the gate electrode
11
. The gate electrode
11
is connected to a gate line (not shown) and the source electrode
15
a
is connected to a data line (not shown). The gate line and the data line cross each other and define a pixel region (not shown). A passivation layer
16
of SiNx, SiO
2
or organic insulating material is formed on the source and drain electrodes
15
a
and
15
b
. The passivation layer
16
has a contact hole
16
c
exposing the drain electrode
15
b
. A pixel electrode
17
of transparent conductive material is formed on the passivation layer
16
at the pixel region. The pixel electrode
17
is connected to the drain electrode
15
b
through the contact hole
16
c.
A second substrate
20
faces and is spaced apart from the first substrate
10
. A black matrix
21
corresponding to the TFT “T” is formed on an inner surface of the second substrate
20
. The black matrix
21
covers portions except the pixel region. A color filter layer
22
is formed on the black matrix
21
. The color filter layer
21
has red (R), green (G) and blue (B) colors that are alternately disposed. One color corresponds to one pixel region. A common electrode
23
of transparent conductive material is formed on the color filter layer
22
. A liquid crystal layer
30
is interposed between the pixel electrode
17
and the common electrode
23
.
The gate insulating layer
12
and the passivation layer
16
of the first substrate
10
and the common electrode
23
of the second substrate
20
are extended to the second region “B”. A seal pattern
40
is formed between the passivation layer
16
and the common electrode
23
to supply a gap for injecting liquid crystal material and prevent the injected liquid crystal material from leaking.
The conventional LCD device is formed through fabricating processes including fabricating an array substrate, fabricating a color filter substrate, and assembling a liquid crystal cell. The array substrate has a TFT and a pixel electrode. The color filter substrate has a color filter layer and a common electrode. The liquid crystal cell assembling process includes attaching the array substrate and the color filter substrate, injecting liquid crystal material, sealing and attaching a polarizing plate.
On the other hand, the conventional LCD device further includes a driving unit to drive the TFT. The driving unit includes a driving integrated circuit (IC) to apply a signal to a line of the LCD device. Packaging methods of the driving IC to the LCD device are classified into a chip on glass (COG) type, a tape carrier package (TCP) type and a chip on film (COG) type. In the COG type, since the driving IC is attached onto an array substrate of the LCD device and an output electrode of the driving IC is directly connected to a pad of the array substrate, the structure and fabricating process are simple, and production cost is low.
FIG. 2
is a plan view showing a conventional LCD device of a COG type.
In
FIG. 2
, the conventional LCD device includes an array substrate
50
and a color filter substrate
60
. The array substrate
50
has a larger area than the color filter substrate
60
. A seal pattern
70
is formed at a boundary of the color filter substrate
60
. Liquid crystal material (not shown) is interposed between the array substrate
50
and the color filter substrate
60
in interior of the seal pattern
70
. The interior of the seal pattern
70
is a display region
51
where images are displayed. In the display region
51
, gate lines
52
and data lines
53
cross each other and define pixel regions. A TFT (not shown) is disposed near a crossing of a gate line
52
and a data line
53
. A gate link line
54
and a data link line
55
are formed at a left edge and a top edge of the array substrate
50
, respectively. One end of the gate link line
54
is connected to the gate line
52
, and the other end of the gate link line
54
is connected to a gate driving IC
81
packaged on the array substrate
50
. One end of the data link line
55
is connected to the data line
53
, and the other end of the data link line
55
is connected to a data driving IC
82
packaged on the array substrate
50
. The gate driving IC
81
and the data driving IC
82
are connected to an external printed circuit board (PCB) (not shown) through a flexible printed circuit (FPC). Since the PCB includes many devices such as ICs, control signals and data signals are generated to drive an LCD device. Here, the PCB may be divided into a gate portion and a data portion, which are connected to each other through a FPC to interchange a gate signal and a data signal.
As mentioned above, the seal pattern
70
supplies a gap between the substrates
50
,
60
for injecting liquid crystal material and prevents the injected liquid crystal material from being leaking. After a specific pattern of heat curable resin is formed on the array substrate
50
, the array substrate
50
and the color filter substrate
60
are aligned and attached through hardening the seal patterning
70
under pressure.
As shown in
FIG. 1
, since a passivation layer
16
(of
FIG. 1
) is formed on an entire surface of an array substrate
10
(of FIG.
1
), the passivation layer
16
(of
FIG. 1
) also exists beneath the seal pattern
40
(of FIG.
1
). Recently, the passivation layer
16
(of
FIG. 1
) is made of organic insulating material such as benzocyclobutene (BCB) of low dielectric constant. Since adhesion of the seal pattern
40
(of
FIG. 1
) to the passivation layer
16
(of
FIG. 1
) of organic insulating material is bad, breakage in the seal pattern
40
(of
FIG. 1
) may occur. Accordingly, when the passivation layer
16
(of
FIG. 1
) is formed of organic insulating material, the passivation layer
16
(of
FIG. 1
) beneath the seal pattern
40
(of
FIG. 1
) should be eliminated to prevent the problems of a breakage.
FIG. 3A
is a schematic magnified plan view of a portion “C” of
FIG. 2
, and
FIG. 3B
is a schematic cross-sectional v
LG.Philips LCD Co. , Ltd.
McKenna Long & Aldridge LLP
Ngo Julie-Huyen L.
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