Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Field effect device in non-single crystal – or...
Reexamination Certificate
2001-05-31
2003-12-16
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Field effect device in non-single crystal, or...
C257S059000, C257S249000, C257S401000
Reexamination Certificate
active
06664569
ABSTRACT:
This application claims the benefit of Korean Patent Application No. 2000-31848, filed on Jun. 9, 2000, the entirety of which is hereby incorporated by reference for all purposes as if fully set forth herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an array substrate for use in a liquid crystal display (LCD) device, and more particularly, an array substrate having a thin film transistor (TFT) with a reduced parasitic capacitance.
2. Discussion of the Related Art
FIG. 1
shows the configuration of a typical TFT-LCD device. The TFT-LCD device
11
includes upper and lower substrates
5
and
22
with an interposed liquid crystal material
14
. The upper and lower substrates
5
and
22
are generally referred to as a color filter substrate and an array substrate, respectively.
On the upper substrate
5
, on a surface opposing the lower substrate
22
, black matrix
6
and color filter layer
7
, including a plurality of red (R), green (G), and blue (B) color filters, are formed in the shape of an array matrix, such that each color filter is surrounded by the black matrix
6
. Also, on the upper substrate
5
a common electrode
18
is formed covering the color filter layer
7
and the black matrix
6
.
On the lower substrate
22
, on a surface opposing the upper substrate
5
, a thin film transistor (TFT) “T”, as a switching device, is formed in the shape of an array matrix corresponding to the color filter layer
7
, and a plurality of crossing gate and data lines
13
and
15
are positioned such that each TFT “T” is located near each crossover point of the gate and data lines
13
and
15
. Also, on the lower substrate
22
a plurality of pixel electrodes
17
are formed in an area defined by the gate and data lines
13
and
15
. The area defined thereby is a pixel region “P”. The pixel electrode
17
is usually formed from a transparent conductive material having good transmissivity, for example, indium-tin-oxide (ITO) or indium-zinc-oxide (IZO).
The pixel and common electrodes
17
and
18
generate electric fields that control the light passing through the liquid crystal cells provided therebetween. By controlling the electric fields, desired characters or images are displayed.
The operation of the TFT-LCD device having the above-mentioned structure is based on the a principle that the alignment direction of the liquid crystal molecules depends on an applied electric field. Namely, the liquid crystal layer having a spontaneous polarization characteristic is a dielectric anisotropy material. The liquid crystal molecules have dipole moments based on the spontaneous polarization when a voltage is applied. Thus, the alignment direction of the liquid crystal molecules is controlled by applying an electric field to the liquid crystal molecules. When the alignment direction of the liquid crystal molecules is properly adjusted, the liquid crystals are aligned and light is refracted along the alignment direction of the liquid crystal molecules to display image data. The liquid crystal molecules function as an optical modulation element having optical characteristics that vary depending upon the polarity of the applied voltage.
FIG. 2
is a plan view illustrating one pixel of an array substrate for the liquid crystal display device according to a related art. As shown, the array substrate includes gate line
13
arranged in a transverse direction; data line
15
arranged in a longitudinal direction perpendicular to the gate line
13
; and a thin film transistor (TFT) “T” as a switching element formed near the crossing of the gate and data lines
13
and
15
. The TFT “T” has a gate electrode
31
, a source electrode
33
and a drain electrode
35
. The gate electrode
31
is extended from the gate line
13
, and the source electrode
33
is extended from the data line
15
. The drain electrode
35
is spaced apart from the source electrode
33
. The source and drain electrodes
33
and
35
respectively overlap both ends of the gate electrode
31
. The TFT “T” also has a semiconductor layer
32
that is made of amorphous silicon (a—Si:H) or poly-silicon.
Moreover, the array substrate further includes a pixel electrode
17
formed on a pixel region “P” that is defined by the gate and data lines
13
and
15
. The pixel electrode
17
is electrically connected with the drain electrode
35
through a drain contact hole
36
, and is usually made of a transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZO). A portion of the pixel electrode
17
overlaps a portion of the gate line
13
such that a storage capacitor “C” is comprised of the pixel electrode
17
and gate line
13
and the interposed dielectric layer (not show).
Still referring to
FIG. 2
, the gate line
13
supplies scanning signals to the gate electrode
31
of the TFT “T” such that the switching element, i.e., the TFT, turns ON. The scanning signals transmitted to the gate line
13
then control the magnitude of the data signals transmitted from the data line
15
to the pixel electrode
17
via the TFT “T.” The data signals of the pixel electrode
17
cause the polarization and re-arrangement of the liquid crystal molecules that are disposed over the pixel electrode
17
. When the scanning signals are not supplied to the gate line
13
, the TFT “T” is turned OFF. At this time, electric charges stored in the pixel are discharged through the TFT “T” and through the liquid crystals. In this discharge phenomenon, if the off resistance is larger or if the pixel area is smaller for improving the resolution, the electric charges stored in the pixel are more rapidly discharged.
In order to solve these problems, the storage capacitor “C” has a parallel connection with the pixel electrode
17
and compensates for electric discharges. Thus, the data signal is maintained in the pixel. At this time, the data signal, however, is affected by source-gate or drain-gate parasitic capacitance. This effect leads to pixel flickering, image retention and non-uniform display.
In general, the parasitic capacitance occurs between the source and gate electrodes
33
and
31
of the TFT “T” or between the drain and gate electrodes
35
and
31
of the TFT “T”. The parasitic capacitance between the source and gate electrodes
33
and
31
is referred to as source-gate or gate-source parasitic capacitance (C
gs
or C
sg
). The parasitic capacitance between the drain and gate electrodes
35
and
31
is referred to as drain-gate or gate-drain parasitic capacitance (C
dg
or C
gd
). When the semiconductor layer
32
is fully saturated by the electric charges, the gate-drain parasitic capacitance C
gd
is increased due to the fact that the electric charges stored in the pixel electrode
17
are transmitted to the drain electrode
35
. Again, this parasitic capacitance causes pixel flickering, the image retention, and gray scale nonuniformity. Thus, it is essentially required to decrease the gate-drain parasitic capacitance C
gd
.
Still referring to
FIG. 2
, the gate electrode
31
is protruded from the gate line
13
over the pixel region “P” near the crossing of the gate and data lines
13
and
15
. The source and drain electrodes
33
and
35
overlap both ends of the gate electrode
31
. In this structure shown in
FIG. 2
, the gate-drain parasitic capacitance C
gd
is defined by an area in which the drain electrode
35
overlaps the gate electrode
31
. Moreover, misalignment often occurs between the gate and drain electrodes
31
and
35
when forming the co-planar source and drain electrodes
33
and
35
over both ends of the gate electrode
31
using a pattern process. Thus, the gate-drain parasitic capacitance C
gd
varies owing to this misalignment between the gate and drain electrodes
31
and
35
. For example, if the width and length of the drain electrode
35
are respectively 30 &mgr;m and 5 &mgr;m, the ratio of the width and the length is 30 to 5. In this case, the overlapped ratio of the drain electrode
35
is usually determined to be 30 to 4, and th
Flynn Nathan J.
LG. Philips LCD Co. Ltd.
McKenna Long & Aldridge LLP
Sefer Ahmed J.
LandOfFree
Liquid crystal display device array substrate and method of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Liquid crystal display device array substrate and method of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Liquid crystal display device array substrate and method of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3180394