Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2002-09-06
2004-08-31
Hjerpe, Richard (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S211000, C345S213000, C345S209000, C345S054000, C345S079000
Reexamination Certificate
active
06784861
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to Liquid-Crystal Display (LCD) devices. More particularly, the invention relates to a LCD device having comparatively long transmission lines for transmitting internal signals, and a method of transmitting signals in the same device.
2. Description of the Related Art
With LCD devices, generally, the controller circuit outputs an image input signal to be displayed, a polarization reverse signal, a horizontal scanning signal, and a vertical scanning signal. The image input signal is taken into the data electrode driver circuit to be synchronized with the horizontal scanning signal. The pixel data signal corresponding to the image input signal thus taken into is polarization-reversed according to the polarization reverse signal and then, it is sent to the respective data electrodes of the LCD panel from the data electrode driver circuit. The vertical scanning signal is taken into the scanning electrode driver circuit. A scanning signal is sent to the scanning electrode driver circuit to be synchronized with the vertical scanning signal by the scanning electrode driver circuit. The pixel data signal is supplied to the specific pixel regions on the panel chosen by the scanning signal, thereby displaying images on the screen of the panel according to the pixel data signal. The data electrode driver circuit comprises a data electrode driver section or sections. The scanning electrode driver circuit comprises a scanning electrode driver section or sections.
FIG. 1
shows the circuit configuration of an example of the prior-art LCD devices of the type described here. This device comprises a LCD panel
1
, a controller circuit
2
, a gray scale power supply circuit
3
, a data electrode driver circuit
4
, and a scanning electrode driver circuit
5
.
The LCD panel
1
includes a color filter for generating color images by dividing each pixel into a sub-pixel of red (R), a sub-pixel of green (G), and a sub-pixel of blue (B). The panel
1
further includes n data electrodes X
1
to Xn (n: a positive integer greater than 2) to be applied with corresponding sub-pixel data signals D, m scanning electrodes Y
1
to Ym (m: a positive integer greater than 2) to be applied with corresponding scanning signals V, and sub-pixel regions (not shown) formed at the respective intersections of the data electrodes X
1
to Xn and the scanning electrodes Y
1
to Ym, The specific sub-pixel regions chosen by the scanning signals V are applied with the corresponding sub-pixel data signals D, thereby displaying color images on the screen (not shown) of the panel
1
according to the signals D.
The controller circuit
2
, which is formed by, for example, an ASIC (Application Specific Integrated Circuit), supplies 8-bit red data DR, 8-bit green data DGr and 8-bit blue data DB to the data electrode driver circuit
4
. These data DR, DG, and DB are supplied to the circuit
2
from the outside of the LCD device. The circuit
2
generates a horizontal scanning signal PH, a vertical scanning signal PV, and a polarization reverse signal POL, based on a horizontal synchronization signal SH and a vertical synchronization signal SV, and so on supplied from the outside of the LCD device. The polarization reverse signal POL is used for alternating-current (AC) driving the panel
1
. The circuit
2
supplies the horizontal scanning signal PH and the polarization reverse signal POL thus generated to the data electrode driver circuit
4
in the voltage mode and at the same time, it supplies the vertical scanning signal PV thus generated to the scanning electrode driver circuit
5
in the voltage mode. Moreover, the circuit
2
supplies a red scale voltage data DGR, a green scale voltage data DGG, and a blue scale voltage data DGB to the gray scale power supply circuit
3
, which are used for giving desired gradation to the data DR, DG, and DB through gamma (&ggr;) compensation, respectively.
The gray scale power supply circuit
3
comprises three digital-to-analog converter (DAC) circuits
11
1
,
11
2
, and
11
3
and 54 voltage follower circuits
12
1
to
12
54
, as shown in FIG.
2
. The DAC circuit
11
1
converts the digital red scale voltage data DGR to 18 analog red scale voltages V
R0
to V
R17
and then, the circuit
11
1
supplies the voltages V
R0
to V
R17
to the voltage follower circuits
12
1
to
12
18
, respectively. Similarly, the DAC circuit
11
2
converts the digital green scale voltage data DGG to 18 analog green scale voltages V
G0
to V
G17
and then, the circuit
11
2
supplies the voltages V
G0
to V
17
to the voltage follower circuits
12
19
to
12
36
, respectively. The DAC circuit
11
3
converts the digital blue scale voltage data DGB to 18 analog blue scale voltages V
B0
to VB
17
and then, the circuit
11
3
supplies the voltages V
B0
to VB
B17
to the voltage follower circuits
12
37
to
12
54
, respectively. The analog red scale voltages V
R0
to V
R17
, the analog green scale voltages V
G0
to V
G17
, and the analog blue scale voltages V
B0
to V
B17
are used for &ggr;-compensation to the red data DR, green data DG, and blue data DB, respectively. The voltage follower circuits
12
1
to
12
54
receive the analog red, green, and blue scale voltages V
R0
to V
R17
, V
G0
to V
G17
, or V
B0
to V
B17
at high input impedance, respectively, and outputs them to the data electrode driver circuit
4
at low output impedance.
The data electrode driver circuit
4
comprises k (k: a natural number) data electrode driver sections
4
l
to
4
k
. Each of the sections
4
l
to
4
k
applies the specific &ggr;-compensation to the red, green, and blue data DR, DG, and/or DE based on the red, green, and blue scale voltages V
R0
to V
R17
, V
G0
to V
G17
, and/or V
B0
to V
B17
to thereby give gradation thereto. Then, the circuit
4
converts the red, green, and blue data DR, DG, and/or DB thus compensated to 384 sub-pixel data signals D and then, outputs the signals D to the data electrodes X
1
to Xn on the panel
1
.
For example, if the panel
1
is designed for the SXGA (Super extended Graphics Array) resolution or mode, the panel
1
has 1280 pixels (horizontal)×1024 pixels (vertical) in total. In this case, the count of the sub-pixels is 3840 pixels (horizontal)×1024 pixels (vertical), because each pixel is formed by three sub-pixels, i.e., a red sub-pixel, a green sub-pixel, and a blue sub-pixel. Here, (3840 pixels)/(384 data signals)=10 (pixels/data signal). Thus, the total number of the data electrode driver sections is 10; i.e., k=10. This means that the data electrode driver circuit
4
comprises 10 data electrode driver sections
4
1
to
4
10
. The following explanation is made under the condition described here.
The data electrode driver sections
4
1
to
4
10
have the same circuit configuration as each other except for the suffixes of the respective elements and the respective signals. Thus, only the section
4
1
is explained below.
The data electrode driver section
4
1
of the data electrode driver circuit
4
comprises three multiplexer (MPX) circuits
13
1
to
13
3
, three 8-bit DAC (Digital-to-Analog Converter) circuits
14
1
to
14
3
, and 384 voltage follower circuits
15
1
to
15
384
, as shown in FIG.
3
.
The MPX circuit
13
1
receives the red scale voltages V
R0
to V
R17
from the gray scale power supply circuit
3
and then, alternately supplies the set of the red scale voltages V
R0
to VR
8
or the set of the red scale voltages V
R9
to V
R17
to the DAC circuit
14
1
according to the polarization reverse signal POL from the controller circuit
2
. Similarly, the MPX circuit
13
2
receives the green scale voltages V
G0
to V
G17
from the power supply circuit
3
and then, alternately supplies the set of the green scale voltages V
G0
to V
G8
or the set of the green scale voltages V
G9
to V
G17
to the DAC circuit
14
2
according to the polarization reverse signal POL. The MPX circuit
13
3
receives the blue scale voltages V
B0
to V
B17
Choate Hall & Stewart
NEC Electronics Corporation
Nguyen Kimnhung
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