Liquid crystal cells – elements and systems – Particular structure – Having significant detail of cell structure only
Reexamination Certificate
1999-09-14
2003-11-18
Dudek, James (Department: 2871)
Liquid crystal cells, elements and systems
Particular structure
Having significant detail of cell structure only
C349S043000, C349S111000, C349S138000
Reexamination Certificate
active
06650389
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a LCD (Liquid Crystal Display) device. In particular, an active-matrix-type LCD device that operates in IPS (In-Plane-Switching) mode, so that a wide range of angles of visual field can be provided. The present invention also relates to a method of manufacturing the LCD device.
2. Prior Arts
There are generally two types of LCD devices: one with the TN (Twisted Nematic) mode and the other with IPS mode. Wherein, according to the TN mode, information is displayed through rotating molecule axes of respective oriented LCD device molecules in a direction perpendicular to a glass substrate, whereas, according to the IPS mode, it is done through rotating the molecule axes in a direction parallel to the glass substrate.
An LCD device with the IPS mode has a feature whereby a high quality display is maintained with less dependency upon the viewing angle. This emanates from the fact that even if the eyes of the viewer are moved, they end up looking at only the short axes of the liquid crystal molecule. This special feature results in providing the benefit of a much wider range of angles of visual field than that provided by an LCD device with the TN mode.
A conventional LCD device with the IPS mode providing a wide range of angles of visual field is disclosed in Publication of Examined Patent Application No. Sho-63-21907 and Publication of Unexamined Patent Application No. Hei-6-202127 (hereafter, referred to as Reference 1 and Reference 2, respectively). According to the LCD devices, as shown in these references, since a voltage, irrelevant to the display voltage corresponding to the image signal, is always applied between data bus lines (drain electrode lines), through which an image signal is transmitted, and its corresponding pixel electrode, the applied voltage causes an occurrence of an unnecessary electric field emitted from the data bus line. Wherein, this unnecessary electric field is applied to a liquid crystal layer. As a result, a problem will occur where the image display quality becomes poor.
Accordingly, in order to prevent the data bus line from emitting the unnecessary electric field, and it being applied to the liquid crystal layer, the LCD device, as illustrated in
FIGS. 1
to
3
(hereafter, referred to as Reference 3) has been developed. Reference 3 is disclosed in Publication of Unexamined Patent Application No. Hei-10-186407 (Patent Application No. Hei-8-286381). Wherein, the data bus line, through which an image signal is transmitted, is formed above a common bus line that a reference voltage is applied to. In other words, by forming the data bus line so that it covers the entire common bus line, it is possible to shield the liquid crystal layer from the said unnecessary electric field.
FIG. 1
illustrates a partial layout of gate bus lines, data bus lines, a common electrode, and a common bus line in the LCD device as disclosed in Reference 3.
FIGS. 2 and 3
are cross-sections along respective straight lines XXI to XXI and XXII to XXII in FIG.
1
.
As illustrated in
FIGS. 2 and 3
, the LCD device is comprised of a glass substrate (hereafter, called TFT substrate)
113
with a matrix of multiple, thin-film transistors (hereafter, called TFT)
106
, a glass substrate (hereafter, called CF substrate)
115
with a color filter layer
122
, and a liquid crystal layer
118
placed between the substrates
113
and
115
. The liquid crystal layer
118
is sealed by a sealing material (not shown in the figures), thus forming liquid crystal cell. This liquid crystal cell is filled with a liquid crystal and spacers.
Gate electrodes
107
of the respective TFT
106
are formed in a matrix on the TFT substrate
113
. Multiple gate bus lines (gate electrode lines)
101
are formed so as to be connected electrically with the respective gate electrodes
107
. Each of the gate bus lines
101
is connected to multiple gate electrodes
107
placed along each line in the TFT matrix. The multiple gate bus lines
101
are placed parallel to one another, and are also extended in the horizontal direction, as shown in FIG.
1
. The gate electrodes
107
and gate bus lines
101
are both covered with a gate insulating film
111
, which is formed on the surface of the TFTs substrate
113
.
A drain electrode
108
and source electrode
109
corresponding to each gate electrode
107
, and a patterned amorphous silicon layer
110
are all formed on the gate insulating film
111
. A prospective to-be-generated, conductive channel, which plays the role of electrically connecting the drain electrode
108
and the source electrode
109
, is formed inside the amorphous silicon layer
110
. The gate electrode
107
, its corresponding drain electrode
108
and source electrode
109
, and a single amorphous silicon layer
110
comprise a TFT
106
.
In addition, as shown in
FIG. 2
, multiple pixel electrodes
104
and multiple data bus lines
102
are formed on the gate insulating film
111
.
As shown in
FIG. 1
, the multiple data bus lines
102
are parallel to one another extending in a vertical direction. Each data bus line
102
electrically connects the multiple drain electrodes
108
along each column in the TFT matrix, to one another.
Each pixel electrode
104
is placed at pixel region P, which is located between two adjacent gate bus lines
101
or between two adjacent data bus lines
102
. It is connected electrically to the source electrode
109
of its corresponding TFT
106
. The pixel electrodes
104
are each strip-shaped, each extending parallel to the data bus line
102
within corresponding pixel region P, in the vertical direction.
The TFT
106
, the pixel electrode
104
, the gate electrode
101
, and the data bus line
102
are, as shown in
FIGS. 2 and 3
, covered with a inter-layer insulating film (passivation film)
112
, which is formed on top of the gate insulating film
111
.
As illustrated in
FIG. 1
, multiple common electrodes
105
, and multiple common bus lines (common electrode lines)
103
extending in the horizontal direction are both formed on the surface of the inter-layer insulating film
112
. Each common electrode
105
is strip-shaped, extending parallel to both the pixel electrode
104
and the data bus line
102
in a vertical direction. Each common bus line
103
connects the multiple common electrodes
105
to one another, and extends parallel to the gate bus line
101
in a horizontal direction.
As clearly shown in
FIG. 1
, each common electrode
105
is placed above its corresponding data bus line
102
, and covers over this entire data bus line
102
. Each common bus line
103
is placed in the vicinity of its corresponding gate bus line
101
, but does not cover this gate bus line
101
.
As shown in
FIG. 2
, a color filter layer
122
is formed on the surface of the CF substrate
115
. The color filter layer
122
is comprised of a color material layer
116
and an over-coating layer
117
, which protects the color material layer
116
and smoothes out the surface of the color filter
122
. The color material layer
116
is comprised of color dot materials or color stripe materials of red, green, and blue, which are arranged and placed according to a certain regulation, and a black matrix
121
, which is placed so as to fill-in among the red, green, and blue dot materials or stripe materials.
A predetermined selecting signal is applied to the gate bus line
101
(see FIG.
4
A). thus switching on its corresponding TFT
106
. Its corresponding image signal is applied (See
FIG. 4B
) to the data bus line
102
selected by the said selecting signal. A common reference voltage is applied to the multiple common bus lines
103
at the same time. The TFT
106
corresponding to the pixel selected by the selecting signal, which is applied to the gate bus line
101
, turns on. As a result, a voltage corresponding to the image signal applied to the data bus line
102
, is applied between its corresponding common electrode
105
and pixel electrode
104
. This applied v
Dudek James
Duong Tai
NEC LCD Technologies Ltd.
Scully Scott Murphy & Presser
LandOfFree
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