Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2000-05-30
2002-01-08
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S718000, C438S719000, C438S720000, C438S725000, C257S059000, C257S247000
Reexamination Certificate
active
06337284
ABSTRACT:
CROSS REFERENCE
This application claims the benefit of Korean Patent Application No. 1999-19145, filed on May 27, 1999, under 35U.S.C. §119, the entirety of which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device fabricated through four photolithography processes and a method of fabricating the same.
2. Description of the Related Art
As shown in
FIG. 1
, a typical liquid crystal display (LCD) device has a gate bus line
60
arranged in a transverse direction and a data bus line
70
arranged in a longitudinal direction, a thin film transistor (TFT) formed near a cross point of the gate bus line
60
and the data bus line
70
. The TFT has a source electrode
70
a,
a drain electrode
70
b,
a gate electrode
60
a,
and a semiconductor layer
80
. The drain electrode
70
b
is connected to a pixel electrode
40
.
The LCD device described above is completed through five photolithography processes.
Hereinafter, a method of fabricating the conventional LCD device will be explained in detail.
FIGS. 2A
to
2
E show a process of manufacturing the conventional LCD device, and
FIGS. 3A and 3B
show a photolithography process to form a gate insulating layer
50
, the amorphous silicon (a-Si) layer
80
a,
and an n-type impurity doped silicon (n
+
a-Si) layer
80
b.
Further,
FIGS. 4A-4C
show a photolithography process to form source and drain electrode
70
a
and
70
b.
First, a gate electrode
60
a
shown in
FIG. 2A
is formed on a transparent substrate
10
during a first photolithography process.
In the first photolithography process, a metal layer (not shown) of Mo or Cr is deposited on the transparent substrate
10
and then a photoresist is applied on the metal layer. Then, a first photo-mask (not shown) is located over the substrate
10
, and light exposure and developing processes are performed to etch the metal layer so that the gate electrode
60
a
is formed. Finally, the photoresist remaining on the metal layer is removed, leaving the gate electrode
60
a
on transparent substrate
10
as shown in FIG.
2
A.
Second, a gate insulating layer
50
, the a-Si layer
80
a,
and a n
+
a-Si layer
80
b
shown in
FIG. 2B
are sequentially formed during a second photolithography process, detailed as shown in
FIGS. 3A and 3B
.
As shown in
FIG. 3A
, a photoresist
88
is applied on the n
+
a-Si layer
80
b.
After that, light exposure and developing processes are performed using a second photo-mask
100
, thereby forming a photoresist pattern
88
a
as shown in FIG.
3
B. The a-Si layer
80
a
and the n
+
a-Si layer
80
b
are simultaneously etched according to the photoresist pattern
88
a
so that the gate insulating layer
50
, the a-Si layer
80
a,
and the n
+
a-Si layer
80
b
are formed. Finally, the photoresist remaining on the n
+
a-Si layer
80
b
is removed.
Third, the source electrode
70
a
and the drain electrode
70
b
shown in
FIG. 2C
are formed during a third photolithography process, detailed as shown in
FIGS. 4A-4C
.
As shown in
FIG. 4A
, a metal layer
170
such as Cr is deposited over the whole surface of the substrate
10
while covering a-Si layer
80
a
and n
+
a-Si layer
80
b.
After that, the positive type photoresist
88
is applied, and then light exposure and developing processes are performed using a third photo-mask
200
, thereby forming a photoresist pattern
88
a
as shown in FIG.
4
B. In accordance with the photoresist pattern
88
a,
a lower metal layer
170
is etched to form the source electrode
70
a
and the drain electrode
70
b
as shown in FIG.
4
C. Continually, the n
+
a-Si layer
80
b
is etched using the metal layer (source and drain electrodes) as a mask. Finally, the photoresist pattern
88
a
remaining on the source electrode
70
a
and the drain electrode
70
b
is removed.
Fourth, the passivation layer
55
having the contact hole
30
shown in
FIG. 2D
is formed during a fourth photolithography process.
An inorganic material such as a nitride or oxide of silicon (SiNx or SiOx, respectively) or an organic material such as bis-benzocyclobutene (BCB) is deposited on the source electrode
70
a
and the drain electrode
70
b.
After that, the positive type photoresist (not shown) is applied, and then light exposure and developing processes are performed using a fourth photo-mask (not shown) to form a photoresist pattern. Then, the passivation layer
55
is formed through an etching process. After the etching process, the photoresist pattern remaining on the passivation layer
55
is removed.
Fifth, the pixel electrode
40
to be connected to the drain electrode
70
b
shown in
FIG. 2E
is formed during a fifth photolithography process.
A metal layer such as indium tin oxide (ITO) is deposited on the passivation layer
55
. After that, the positive type photoresist (not shown) is applied, and then light exposure and developing processes are performed using a fifth photo-mask (not shown), thereby forming a photoresist pattern. In accordance with the photoresist pattern, the metal layer is etched so that the pixel electrode
40
is formed. After the etching process, the photoresist pattern remaining on the pixel electrode
40
is removed.
The photolithography process described above includes the steps of: cleaning a substrate; applying a photoresist; soft-baking the photoresist; aligning a photo-mask; light-exposing the photoresist; developing the photoresist; inspecting the array substrate; hard-baking the photoresist; etching a portion that the photoresist does not cover; inspecting the array substrate; and removing the photoresist.
Since the photolithography process includes the complex steps described above, as the number of photolithography processes increases, the inferiority rate become greater, leading to a low yield. In other words, reliability of the manufacturing process varies inversely proportional to the number of photolithography processes performed.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a liquid crystal display device fabricated through four photolithography processes.
Another object of the present invention is to increase yield and to reduce the production cost of TFT fabrication.
To achieve the above objects, the present invention provides a method of manufacturing a liquid crystal display device including a first photolithography process forming a gate electrode on a substrate; a second photolithography process including: a) depositing sequentially a gate insulating layer, first and second semiconductor layers, and a metal layer; b) applying a first photoresist on the metal layer; c) aligning a first photo mask with the substrate; d) light exposing and developing the first photoresist to produce a first photoresist pattern; e) etching the metal layer using a first etchant, the first etchant ashing the first photoresist pattern on a predetermined portion of the metal layer to produce a second photoresist pattern, thereby exposing the predetermined portion of the metal layer; and f) etching the gate insulating layer, the first and second semiconductor layer, and the predetermined portion of the metal layer using a second etchant according to the second photoresist pattern to form source and drain electrodes, an ohmic contact layer, and an active area; a third photolithography process forming a passivation film and a contact hole; and a fourth photolithography process forming a pixel electrode contacting with the drain electrode through the contact hole.
The first etchant contains Cl
2
/O
2
gas and the second etchant contains SF
6
/HCl or SF
6
/H
2
/Cl
2
gas. The source and drain electrodes are made of a metal selected from a group consisting of Cr, Mo, Al, and Al alloy, and the first semiconductor layer comprises an amorphous silicon and the second semiconductor layer comprises an amorphous silicon doped with n-type impurity.
REFERENCES:
patent: 5427962 (1995
Han Changwook
Hwang Kwangjo
Deo Duy-Vu
LG. Philips LCD Co. Ltd.
Long Aldridge & Norman LLP
Utech Benjamin L.
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