Liquid crystal cells – elements and systems – Particular structure – Having significant detail of cell structure only
Reexamination Certificate
1999-09-07
2001-07-31
Sikes, William L. (Department: 2871)
Liquid crystal cells, elements and systems
Particular structure
Having significant detail of cell structure only
C349S042000, C349S139000, C349S149000, C349S156000
Reexamination Certificate
active
06268898
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a liquid crystal display device. In particular, one where the existence or non-existence, shape, etc. of the transfer column can be observed without forming a monitoring window. The present invention also relates to a method of manufacturing the liquid crystal display device.
2. Prior Arts
Hereafter, the conventional liquid crystal display devices will be described with reference to the Figures.
FIG. 1
is an aerial view showing the configuration of the conventional liquid crystal display device from the viewpoint of the display surface side, and
FIG. 2
is an equivalent circuit diagram illustrating the structure outline of this type of liquid crystal display device.
As shown in
FIG. 1
, the active matrix-type liquid crystal display device, which uses Thin-Film Transistors (hereafter, TFTs) as switching elements, is composed of a TFTs substrate
100
and a color filter substrate
20
. Wherein, the TFTs substrate
100
has TFTs and pixel electrodes
30
arranged in matrix form, whereas the color filter substrate
20
is made of a shielding film (namely a black matrix)
23
, a coloring layer, and a common electrode. The above two substrates
100
and
20
face each other across a liquid crystal.
In
FIG. 2
, reference numeral
41
depicts gate lines or scanning lines driven by a gate bus line driver (not shown in the Figure), which is connected to the gate terminals
31
. Reference numeral
42
depicts drain bus lines or signal lines driven by a drain bus driver (not shown in the Figure), which is connected to the drain terminals
32
. Reference numeral
47
depicts TFTs, where their gates are connected to the gate bus line
41
, and their drains are connected to the drain bus lines
12
. Reference numeral
46
depicts pixel electrodes, which are connected to the respective TFTTs
47
, and which are formed of a transparent conductive film such as ITO.
The area of a color filter substrate
20
is overlapped with a partial area of the TFTs array substrate
100
, wherein the substrates
20
and
100
face each other across a liquid crystal, as is mentioned above.
Each accumulation capacitor element
45
and liquid crystal capacitor element
44
, are connected parallel to each other. In addition, they are connected to their corresponding TFT
47
in series. Each accumulation capacitor element
45
is formed of a pixel electrode
46
and an accumulation capacitor electrode (not shown in the Figure), where an insulating film is sandwiched between these electrodes. Whereas, each liquid crystal capacitor element
44
is formed of a pixel electrode
46
and an electrode (not shown in the Figure) facing the electrode
16
, which is located on the surface of the color filter substrate
20
; wherein the liquid crystal is sandwiched between the above two electrodes. In result, the common voltage, which is input from the common voltage input terminals
33
and formed on the surface of the TFTs array substrate
100
, is supplied from the transfer pads to the respective, facing electrodes via the transfer columns
27
.
The structure and manufacturing method of the representative conventional TFTs array substrate will be described with reference to
FIGS. 3 and 4
.
FIG. 3
is an aerial view showing the structure of a pixel section, according to the first example of conventional TFTs array substrates, and
FIG. 4
is a cross section of
FIG. 3
cut along the line of A-A′.
In
FIGS. 3 and 4
, first of all, a gate electrode
1
, a gate bus line
11
(see
FIG. 3
) and an accumulation capacitor electrode are formed on top of the glass substrate
101
by patterning the first metal film, made of a metal such as Cr or Al. In addition, in
FIG. 3
, a part of the gate bus line
11
also acts as an accumulation capacitor electrode. Afterwards, a gate insulating film
14
, made of a material such as silicon oxide film or silicon nitride film; a channel layer
2
, made of intrinsic semiconductor non-crystalline silicon (hereafter, [a-Si (I)]); and a contact layer
7
, made of n-type semiconductor non-crystalline silicon (hereafter, [a-Si (n+)]), are successively formed. Next, the patterning process etches off part of the gate insulating film
14
; wherein, the part corresponds to the regions (not shown in the Figures) where terminals used for interfacing with a driver IC are to be formed. Then, a through-hole (not shown in the Figures), which is used to electrically interface a first metal film comprising the gate electrode
1
with a second metal film (where a drain electrode
3
, a source electrode
4
, and a drain bus line
12
are to be formed from this second metal film later), is formed. Afterwards, in the same way as the gate electrode
1
, the second metal film, made of a metal such as Cr or Al, is patterned, so as to form the drain electrode
3
, the source electrode
4
, and the drain bus line
12
. A transparent conductive film consisted of a transparent conductive material such as ITO, is formed as a pixel electrode
6
. Subsequently, the contact layer
7
is etched, so as to remove part of its area on top of the channel layer
2
. Afterwards, by the formation of a passivation film
15
, which is made of a material such as silicon nitride, the TFTs array substrate
100
is completed. It is noted that the passivation film
15
located on top of the pixel electrode
6
is removed, in order to prevent a drop in device transmittance, namely a drop in brightness of the display, which causes the absorption of light for the passivation film
15
. That is to say, as shown in
FIGS. 3 and 4
, a passivation film aperture region is provided to cover almost the entire surface of the pixel electrode
6
.
Next, the structure and manufacturing method of the transfer pad, which is formed on top of the first example of conventional TFTs array substrates, will be explained hereafter, with reference to the Figures.
FIG. 5
is an aerial view showing the configuration of the transfer pad formed on top of the first example of conventional TFTs array substrates, and
FIG. 6
is a cross section of
FIG. 5
cut along the line of A-A′. The manufacturing method and process described below, is the same as the TFTs array substrate described earlier with reference to
FIGS. 3 and 4
.
In
FIGS. 5 and 6
, first of all, a first metal film
301
, which is made of a metal such as Cr or Al, is formed. It is then patterned into the shape of a transfer pad. Afterwards, a gate insulating film
14
, made of a material such as silicon oxide or silicon nitride, is formed on top of the glass substrate
101
. Then, a patterning process etches off a predetermined area of the gate insulating film
14
on top of the first metal film
301
, so as to form the through hole
9
, which is used to electrically interface the first metal film
301
with the second metal film
303
. Next, the second metal film
303
, made of a metal such as Cr or Al, is patterned into a fixed shape in the same way as the first metal film
301
. Next, the transparent conductive film
306
, made of a transparent conductive material such as ITO, is formed on top of the second metal film
303
mentioned above. Subsequently, through the formation of the passivation film
15
, made of a material such as silicon nitride, the transfer pad is formed. At this point, the passivation film
15
, located on the surface of the transparent conductive film
306
, is removed to electrically connect the transfer pad and transfer column
24
. Namely, as shown in
FIGS. 5 and 6
, the aperture region of the passivation film
15
is provided on top of the transparent conductive film
306
. This transfer pad is connected to the common voltage input terminal
33
(see FIGS.
1
and
2
), via one or both of the first or second metal films
301
and
303
.
In the first example of conventional TFTs array substrates, previously described with reference to
FIGS. 3 and 4
, the drain bus line
12
and the pixel electrode
6
are both formed on top of the gate insulating fi
NEC Corporation
Ngo Julie
Sikes William L.
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