Liquid crystal cells – elements and systems – Particular excitation of liquid crystal – Electrical excitation of liquid crystal
Reexamination Certificate
1999-10-25
2002-07-02
Ton, Toan (Department: 2871)
Liquid crystal cells, elements and systems
Particular excitation of liquid crystal
Electrical excitation of liquid crystal
C349S044000, C438S030000
Reexamination Certificate
active
06414730
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a liquid crystal display device for displaying images and characters using liquid crystal and a method for manufacturing the same.
2. Description of the Related Art
There are known active matrix type display devices as an above-mentioned type liquid crystal display device, in which switching elements such as thin film transistors (hereinafter referred to as “TFTs”) are provided on one of a pair of substrates disposed so as to confront each other with a liquid crystal layer between to apply an electric field to each pixel.
FIG. 12
is a schematic diagram of a configuration of an active matrix substrate
1
which is one of substrates of a liquid crystal display device using TFTs. In the liquid crystal display device are formed TFTs
2
of switching elements and pixel capacities
3
in a matrix form. A plurality of gate signal lines
4
and source signal lines
5
are disposed so as to intersect each other at right angles. The gate signal lines
4
are connected to the gate electrodes of the TFTs
2
which are driven by signals inputted thereto. The source signal lines
5
are connected to the source electrodes of the TFTs
2
to input video signals thereto. Pixel electrodes
7
which are electrodes of the pixel capacities
3
at one side thereof are connected to drain electrodes
6
of the TFTs
2
. Electrodes of the pixel capacities at the other side thereof are counter electrodes disposed on a counter substrate which faces the active matrix substrate
1
when the liquid crystal display device is formed.
FIG. 13
is a plan view showing a structure of the active matrix substrate
1
.
FIG. 14A
is a sectional view taken along line A
1
—A
1
in FIG.
13
.
FIG. 14B
is a sectional view taken along line B
1
—B
1
in FIG.
13
.
FIG. 14C
is a sectional view taken along line C
1
—C
1
in FIG.
13
. The active matrix substrate
1
comprises gate electrodes
11
, gate signal lines
4
, a semiconductor layer
13
, an n
+
-Si layer to become source electrodes
8
and drain electrodes
6
, a metal layer to become source signal lines
5
and source and drain extraction electrodes
14
and
15
, an interlayer insulation film
16
and a transparent conductive film (ITO: indium tin oxide) to become the pixel electrodes
7
which are sequentially formed on a transparent insulating substrate
10
. The pixel electrodes
7
are connected to the drain electrodes
6
of the TFTs via through holes
21
extending through the interlayer insulation film
16
and the drain extraction electrodes
15
. Gate terminals
22
and source terminals
23
are provided at the ends of the gate signal lines
4
and source signal line
5
, respectively.
Since the interlayer insulation film
16
is interposed between the gate signal lines
4
and source signal lines
5
and the pixel electrodes
7
, the pixel electrodes
7
can overlap upon the signal lines
4
and
5
. Such a structure is disclosed in, for example, Japanese Unexamined Patent Publication JP-A 58-172685 (1983) and is known to be effective, for example, in improving a numerical aperture and suppressing poor alignment of liquid crystal by shielding an electrical field generated by the signal lines.
An example of manufacturing steps for the active matrix substrate
1
.
The gate signal lines
4
and gate electrodes
11
are first fabricated on the transparent insulating substrate
10
, and the gate insulation film
12
to allow the source signal lines
5
to overlap, an i-Si layer to become the semiconductor layer
13
and the n
+
-Si layer to become the source electrodes
8
and drain electrodes
6
are continuously formed. Subsequently, n
30
-Si layer to become the source electrodes
8
and drain electrodes
6
and the semiconductor layer
13
to cause TFT operations are patterned. Masked etching is carried out to form the contact holes
20
to establish electrical contact with the gate electrodes
11
on the gate insulation film
12
in order to allow input of further signals. The steps up to this point are related to formation of the gate terminals
22
as shown in FIG.
14
B.
Next, the metal layer to become the source extraction electrodes
14
, the source signal lines
5
and drain extraction electrodes
15
is fabricated; the interlayer insulation film
16
is formed to insulate them from the pixel electrodes
7
; and masked etching is carried out to form contact holes
24
for inputting signals to the source signal lines
5
and the through holes
21
for inputting signals to the drain extraction electrodes
15
. The steps up to this point form the source terminals as shown in FIG.
14
C.
Finally, the transparent conductive film to become the pixel electrodes
7
is formed to form the section as shown in FIG.
14
A. The fabrication of the active matrix substrate
1
is thus completed.
The recent trend toward larger and high resolution liquid crystal display devices has resulted in demands for wiring with low resistance metallic material. Aluminum films or aluminum alloy films primarily constituted by aluminum have come to attention as low resistance metal wiring materials because they are relatively inexpensive and are easy to form. Another pressing need is to reduce manufacturing steps in order to fabricate liquid crystal displays with high quality at low cost to achieve price reduction.
The above-described method for manufacturing the active matrix substrate
1
for the liquid crystal display device requires two masked etching steps, i.e., the step of performing masked etching on the gate insulation film
12
to form the contact holes
20
in order to form the gate terminals
22
and the step of performing masked etching on the interlayer insulation film
16
to form the contact holes
24
for the source terminals
23
and the through holes
21
for connecting the pixel electrodes
7
. On the contrary, the number of times of the masked etching can be reduced to one, for example, by performing the step of forming the contact holes
20
in the gate insulation film
12
and the step of forming the contact holes
23
and through holes
21
in the interlayer insulation film simultaneously to fabricate a liquid crystal display device at a low cost. For example, such a method of manufacture is disclosed in Japanese Unexamined Patent Publication JP-A 9-73100 (1997). According to this publication, the number of steps can be reduced by using a metal film as an etching stopper layer to provide selectivity during the etching of an insulation film. Aluminum, titanium, chromium and alloys of them are named as metals having such a function.
It is possible to propose a method in which an aluminum film or an aluminum alloy film primarily made of aluminum, which serves also as a low resistance metal film, is formed on the drain extraction electrodes
15
, for example, simultaneously performing the step of forming the contact holes
20
in the gate insulation film
12
and the step of forming the contact holes
24
and through holes
21
in the interlayer insulation film
16
, as proposed in Japanese Unexamined Patent Publication JP-A 9-73100 (1997).
However, since the aluminum film or aluminum alloy film primarily made of aluminum which serves as an etch stopper layer and a low resistance metal film can not contact the transparent conductive film (ITO) as the pixel electrodes
7
, the low resistance metal film on the drain extraction electrodes
15
which face the through holes
21
must be removed by means of wet etching after the through holes
21
are formed. However, since wet etching is anisotropic etching, side etching (over-etching) occurs under the interlayer insulation film
16
as shown in
FIG. 15
, which results in the formation of a step
25
. As shown in
FIG. 13
, since the bottom of the through hole
21
is formed smaller than the end of the drain extraction electrode
15
such that the drain extraction electrode
15
is exposed on the entire area of the bottom, a side etch region
26
as a result of the wet etching is formed along the entire circum
Akamatsu Keiichi
Shimada Yoshinori
Chung David
Niixon & Vanderhye P.C.
Sharp Kabushiki Kaisha
Ton Toan
LandOfFree
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