Liquid crystal cells – elements and systems – Particular excitation of liquid crystal – Electrical excitation of liquid crystal
Reexamination Certificate
2000-09-08
2003-06-17
Kim, Robert H. (Department: 2871)
Liquid crystal cells, elements and systems
Particular excitation of liquid crystal
Electrical excitation of liquid crystal
C438S030000
Reexamination Certificate
active
06580474
ABSTRACT:
This application claims the benefit of Korean Patent Application No. 1999-38017, filed on Sep. 8, 1999, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, to a device and method for fabricating the LCD device having a thin film transistor (TFT).
2. Discussion of the Prior Art
Generally, an LCD device includes top and bottom glass substrates and a liquid crystal injected therebetween. On the bottom glass substrate, a plurality of gate lines extending in one direction and a plurality of data lines extending in a perpendicular direction are formed. In this matrix arrangement, a plurality of TFTs are disposed near the crossover points of the data and gate lines.
On the top glass substrate, red (R), green (G) and blue (B) color filter layers and a common electrode are disposed. Generally, a light shielding layer (black matrix) is formed on the top glass substrate and a pair of polarizers are disposed on the outer surfaces of the top and bottom glass substrates to selectively transmit light.
A conventional LCD device will be described in detail below with reference to
FIG. 1
, which is a plan view of a conventional LCD device.
As illustrated in
FIG. 1
, the conventional LCD device includes a plurality of gate lines
22
formed on a transparent substrate, a plurality of data lines
24
perpendicularly crossing the gate lines
22
, a plurality of TFTs “S” formed near the crossover points of the gate and data lines
22
and
24
, and a plurality of pixel electrodes
14
connected to the TFTs “S”. The gate lines
22
are separated by intervals from each other and extend in one direction, whereas the data lines
24
are separated by intervals from each other and extend in a perpendicular direction to the gate lines
22
. Each end portion of gate and data lines
22
and
24
has gate and data pads
21
and
23
, respectively. A storage capacitor “Cst” is arranged on a predetermined portion of the gate line
22
. Two adjacent gate lines
22
and two adjacent data lines
24
define the boundaries of a pixel region. In each pixel region, a TFT “S” and a pixel electrode
14
are disposed.
Each TFT includes a gate electrode
26
, a source electrode
28
and a drain electrode
30
. A gate insulating layer is formed between the gate and source electrodes
28
and
30
and between the gate and drain electrodes
26
and
30
. The gate electrode
26
extends from the gate line
22
and the source electrode
28
extends from the data line
24
. The drain electrode
30
connects the pixel electrode
14
through a contact hole
31
.
The TFT transmits a signal of the data line
24
to the pixel electrode
14
in response to a signal of the gate line
22
.
In the conventional LCD device having the above-described TFTs, if a signal voltage is applied to the gate electrode
26
, the TFT is turned on so as to transmit a data voltage representing picture data to the pixel electrode
14
and the liquid crystal.
FIGS. 2A
to
2
E show fabrication process steps of an active matrix liquid crystal display device according to the conventional art.
First, a first metal layer is deposited on a substrate
1
by a sputtering process after a cleaning process in order to remove organic materials and alien substances from the substrate
1
, thereby enhancing adhesion between the substrate
1
and the metal layer.
FIG. 2A
shows a step for forming a gate electrode
26
and a first capacitor electrode
22
by patterning the first metal layer using a first mask.
A low resistance metal such as aluminum is used to form the gate electrode
26
so as to reduce the RC delay. However, pure aluminum has weak resistance to most enchants and may result in line defects due to a formation of a hillock during a high temperature process. Thus, an aluminum alloy is used. And in some cases, a double layered gate is used wherein another metal layer covers the aluminum or aluminum alloy.
A gate insulating layer
50
is deposited on the whole surface of the substrate
1
covering the gate and capacitor electrodes
26
and
22
. Then, a pure amorphous silicon (a-Si:H) layer
52
and a doped amorphous silicon (n
+
a-Si:H) layer
54
are deposited sequentially on the gate insulating layer
50
.
As shown in
FIG. 2B
, an active layer
55
and a semiconductor island
53
are formed by patterning the silicon layers
52
and
54
using a second mask. The doped amorphous silicon layer
54
(i.e. ohmic contact layer) reduces the contact resistance between the active layer
55
and an electrode which is formed later.
FIG. 2C
shows a step for forming a data line
24
, source and drain electrodes
28
and
30
by depositing a second metal layer. At the same time, a second capacitor electrode
58
is formed on the gate insulating layer
50
, covering a portion of the first capacitor electrode
22
.
Then, the ohmic contact layer between the source and drain electrodes
28
and
30
is etched using the source and drain electrodes
28
and
30
as a mask.
As depicted in
FIG. 2D
, an insulating layer is deposited on the entire surface of the substrate
1
covering the source and drain electrodes
28
and
30
. The insulating layer is patterned using a fourth mask to form a protection film
56
. The protection film
56
may be selected from inorganic materials such as SiN
x
and SiO
2
or organic materials such as a BCB (benzocyclobutene). In addition, a material having a high light transmittance, humidity resistance and durability is used to form the protection film
56
in order to protect the channel area of the TFT and major portions of a pixel region from possible exposure to humidity and scratches during later processing steps.
Further, a data pad contact hole
33
is formed on the data pad
23
, and drain and capacitor contact holes
31
and
59
are formed on the drain electrode
30
and the second capacitor electrode
58
, respectively.
FIG. 2E
shows a step for forming a pixel electrode
14
by depositing a transparent conducting oxide (TCO) layer
15
and patterning it using a fifth mask. Indium tin oxide (ITO) is usually employed for the transparent conducting oxide layer. The pixel electrode
14
contacts the second capacitor electrode
58
through the capacitor contact hole
59
and the drain electrode
30
through the drain contact hole
31
. Another portion of the transparent conducting oxide layer
15
is also formed contacting the data pad
23
through the data pad contact hole
33
.
As described, the conventional art requires at least five masks in fabricating the TFT array panel of the LCD device, and each mask process requires many steps such as cleaning, depositing, baking and etching. Therefore, if the number of mask processes is reduced, even if only by one, then production would be increased and cost would be decreased.
SUMMARY OF THE INVENTION
Therefore it is an object of the present invention to provide a thin film transistor array panel of a liquid crystal display device and methods of forming the same that eliminates the problems of conventional methods.
A further object of the present invention is to fabricate the liquid crystal display device with a high yield and a reduced fabrication time. The present invention provides, in one embodiment, a method for fabricating a liquid crystal display array panel, comprising the steps of: forming a gate line by depositing a first metal layer on a substrate and patterning the first metal layer using a first mask; depositing an insulating layer, a pure amorphous silicon layer, a doped amorphous silicon layer and a second metal layer sequentially on the entire surface of the substrate and covering the gate line; forming a data line region, a gate line protection layer and an active area by patterning the second metal layer and the doped amorphous silicon layer using a second mask, the data line region having a source electrode and the gate line protection layer having a drain electrode spaced at a predetermined distance from the source electr
Ahn Byung Chul
Ha Young Hun
Kim Yong Wan
Lim Byung Ho
Yoo Soon Sung
Birch & Stewart Kolasch & Birch, LLP
Di Grazio Jeanne A.
Kim Robert H.
LG. Philips LCD Co. Ltd.
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