Liquid crystal cells – elements and systems – Particular structure – Having significant detail of cell structure only
Reexamination Certificate
2002-09-19
2003-11-25
Kim, Robert H. (Department: 2871)
Liquid crystal cells, elements and systems
Particular structure
Having significant detail of cell structure only
C349S138000, C349S147000, C438S030000
Reexamination Certificate
active
06654091
ABSTRACT:
This application claims the benefit of Korean Patent Application No. 2000-8042, filed on Feb. 19, 2000, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, to an active matrix LCD (AM-LCD) device having thin film transistors (TFTs).
2. Discussion of the Related Art
Because liquid crystal display (LCD) devices are light, thin, and consume low power they are widely used in office automation equipment and video devices. LCDs are based on the optical anisotropy of a liquid crystal (LC). A LC has long, thin molecules whose orientational alignment can be controlled by an applied electric field. When the alignment of the LC molecules is correct, an applied light is refracted along the alignment direction of the LC molecules such that an image is displayed.
Active matrix (AM) LCDs, in which thin film transistors (TFTs) and pixel electrodes are arranged in an array matrix, are typically used because of their high resolution and superiority in displaying moving images. In an AM LCD each TFT serves as a switch for a corresponding pixel. A switched on pixel transmits incident light. Since amorphous silicon is relatively easy to form on large, relatively inexpensive, glass substrates, amorphous silicon thin film transistors (a-Si:H TFT) are widely used.
FIG. 1
is a cross-sectional view illustrating a conventional LCD panel
20
. As shown, the LCD panel has lower and upper substrates
2
and
4
, and an interposed liquid crystal layer
10
. The lower substrate
2
includes a substrate
1
, a TFT “S” as a switching element to selectively change the orientation of the liquid crystal molecules, and a pixel electrode
14
for the application of a voltage that produces an electric field across the liquid crystal layer
10
in accordance with signals from the TFT “S”. The upper substrate
4
has a color filter
8
for implementing color. A common electrode
12
is formed on the color filter
8
. The common electrode
12
serves as the other electrode for producing the electric field across the liquid crystal layer
10
. The pixel electrode
14
is arranged over a pixel portion “P”, i.e., a display area. Further, to prevent leakage of the liquid crystal layer
10
between the substrates
2
and
4
, the substrates
2
and
4
are sealed by a sealant
6
. The nematic, smectic, and cholesteric liquid crystals are most widely used in the above-mentioned LCD panel.
FIG. 2
is a plan view illustrating the lower substrate
2
of the typical LCD device shown in FIG.
1
. As shown, on a substrate (reference
1
of Figure), a gate line
22
is arranged in a transverse direction, and a data line
24
is arranged perpendicular to the gate line
22
. The TFT “S” is arranged at a crossing point of the gate and data lines
22
and
24
. The pixel electrode
14
is arranged on a pixel region (reference “P” of
FIG. 1
) defined by the gate and data lines
22
and
24
. The TFT “S” includes a gate electrode
26
, a source electrode
28
and a drain electrode
30
. The gate electrode
26
electrically connects with the gate line
22
, and the source electrode
28
electrically connects with the data line
24
. The drain electrode
30
electrically connects with the pixel electrode
14
through a drain contact hole
32
.
Still referring to
FIG. 2
, gate and data pads
21
and
23
are integrally formed as terminal portions of the gate and data lines
22
and
24
, respectively. Over the gate and data pads
21
and
23
are a gate pad electrode
34
and a data pad electrode
36
. The gate and data pads
21
and
23
are electrically connected with the gate pad electrode
34
and the data pad electrode
36
via a gate pad contact hole
44
and a data pad contact hole
42
, respectively. The gate pad electrode
34
and the data pad electrode
36
are electrically connected with external driving circuits (not shown) that drive the TFT “S” and the pixel electrode
14
.
In addition, a storage capacitor “Cst” is formed over a portion of the gate line
22
. The storage capacitor “Cst” stores electric charge. When an electric signal is applied to the gate electrode
26
of the TFT “S”, a data signal can be applied to the pixel electrode
14
. Thus, unless the electric signal is applied to the gate electrode
26
, a data signal cannot be applied to the pixel electrode
14
.
A process for manufacturing the array substrate
2
requires repeated steps of depositing and patterning of various layers. The patterning steps use photolithography masks to control light exposing. As each photolithography step requires a mask, the number of masks required controls the number of patterning steps. As the number of masks decreases, the fabricating process becomes simpler and fewer errors tend to occur.
The fabricating process for the array substrate is determined by the design specifications for the array substrate and the materials used for the various layers. For example, when fabricating a large (say above about 12 inches) LCD device, the resistance of the gate line material can be a critical factor in determining the quality of the LCD device. Therefore, a highly conductive metal, such as aluminum (AL) or an aluminum alloy, is usually used for the gate lines of large LCD devices.
The general manufacturing process for the lower substrate
2
will be explained with reference to
FIGS. 3A
to
3
E. In practice, an inverted staggered type TFT is widely employed due to its advantages of simplicity and high quality. The inverted staggered type TFT can be classified as either a back-channel-etch type or an etching-stopper type, based on the method of forming a channel. As the back-channel-etch type has a simpler structure,
FIGS. 3A
to
3
E show a manufacturing process that produces back-channel-etch type TFTs.
FIGS. 3A
to
3
E are sequential cross sectional views taken along lines “A—A” and “B—B” of FIG.
2
. At first, extraneous substances and organic materials are removed from a substrate
1
. By cleaning the substrate
1
the adhesion between the substrate
1
and subsequently formed layers is increased. After cleaning, a first metallic material is deposited on the substrate
1
and patterned via photolithography using a first mask to produce a gate electrode
26
, a gate line (not shown in
FIG. 3A
, but reference element
22
of FIG.
2
), and a first capacitor electrode
22
a
. Aluminum (Al) is a widely used first metallic material because it has a low resistance that reduces RC delays. However, pure aluminum often produces hillocks that can cause defects. Therefore, an aluminum alloy (or an aluminum layer that is covered by another metal) is usually used instead of pure aluminum.
Next, as shown in
FIG. 3B
, a gate insulating layer
50
is deposited on the exposed surface of the substrate
1
such that the gate insulating layer
50
covers the gate line, including the gate electrode
26
, and the first capacitor electrode
22
a
. Thereafter, a pure amorphous silicon layer (a-Si:H)
52
and a doped amorphous silicon layer (n
+
a-Si:H)
54
are sequentially deposited on the gate insulating layer
50
. The amorphous silicon layer and the doped amorphous silicon layer
52
and
54
are then patterned into an active layer
55
and a semiconductor island
53
, using a second mask. The doped amorphous silicon layer
54
reduces the contact resistance between the active layer
55
and a metal layer that will be subsequently formed over the active layer
55
. The doped amorphous silicon layer
54
is often called an ohmic contact layer.
Subsequently, as shown in
FIG. 3C
, a second metallic material is deposited and patterned using a third mask into source and drain electrodes
28
and
30
, a data line
24
(also see FIG.
2
), and a second capacitor electrode
58
. Beneficially, the second metallic material is either chromium (Cr) or a chromium alloy. The second capacitor
58
is formed on the gate insulating layer
50
and overlaps a portion of the first capacitor electrode
22
a
. This forms t
Moon Kyo-Ho
Yoo Soon-Sung
Kim Robert H.
LG. Philips LCD Co., Ltd
McKenna Long & Aldridge
Qi Mike
LandOfFree
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