Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1998-04-28
2001-06-12
Shalwala, Bipin (Department: 2778)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S100000, C345S204000
Reexamination Certificate
active
06246385
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a liquid crystal display device useful as a display for video appliance, computer or other information equipment, and more particularly to a liquid crystal display device and liquid crystal driving method for driving so as to minimize luminance unevenness of each pixel.
BACKGROUND OF THE INVENTION
FIG. 49
is a block diagram of a conventional liquid crystal display device showing an equivalent circuit of a liquid crystal panel and a drive circuit for driving this liquid crystal panel. This liquid crystal display device comprises a liquid crystal panel
14
, an upper signal line drive circuit
15
, a lower signal line drive circuit
16
, a scanning line drive circuit
17
, a control circuit
18
, and a drive power source circuit
19
.
The liquid crystal panel
14
has plural signal lines provided in the y-direction (vertical direction) and plural scanning lines provided in the x-direction (horizontal direction). The signal line is composed of upper signal line
10
and lower signal line
11
divided equally in the vertical direction, and the number of upper and lower signal lines
10
,
11
is M each. The number of scanning lines
12
is 2N. The addresses of the upper and lower signal lines
10
,
11
are supposed to be Y
1
to YM, the addresses of the upper half scanning line
12
to be X
1
to XN, and the addresses,of the lower half scanning line
12
to be XN+1 to X
2
N.
In the liquid crystal panel
14
of such simple matrix type, the upper signal lines
10
, lower signal lines
11
, and scanning lines
12
are arranged in a matrix, and a pixel
13
is formed each at the intersection of upper signal line
10
and scanning line
12
, and the intersection of lower signal line
11
and scanning line
12
. The pixel
13
has a liquid crystal cell and a transparent pixel electrode, or a driving terminal including liquid crystal cell and transparent pixel electrode, and its capacitance is determined by the liquid crystal cell and pixel electrode. Herein, the capacitance of the pixel
13
is called the pixel capacitance. Incidentally, in the case of a TFT type liquid crystal panel, for example, the pixel includes TFT, liquid crystal cell and others.
This liquid crystal panel
14
is driven as being divided into upper and lower halves. That is, the upper signal line
10
is driven by an upper signal line drive circuit
15
, and the lower signal line
11
by a lower signal line drive circuit
16
. The scanning line
12
is driven from one end side of the scanning line
12
by one scanning line drive circuit
17
.
The liquid crystal panel
14
shown in
FIG. 49
is driven from the left end of the scanning line
12
, and such driving method of driving each pixel
13
by applying a driving voltage to the scanning line
12
from one end is called the scanning line one-end drive. The upper signal line drive circuit
15
and lower signal line drive circuit
16
are disposed around the liquid crystal panel
14
depending on the number of upper signal lines
10
and lower signal lines
11
and the number of scanning lines
12
.
The control circuit
18
is a control circuit for controlling the upper signal line drive circuit
15
, lower signal line drive circuit
16
, and scanning line drive circuit
17
on the basis of an input image signal. The drive power source circuit
19
is a circuit for supplying a driving voltage to the upper signal line drive circuit
15
, lower signal line drive circuit
16
, and scanning line drive circuit
17
. Herein, there are five driving voltages, V(+), V(−), VH, Vref, and VL, and the pixels
13
are driven by the combination thereof.
The scanning line drive circuit
17
, for upper and lower divided driving of signal lines, scans parallel the scanning lines
12
of addresses X
1
to XN and scanning lines
12
of addresses XN+1 to X
2
N. That is, the scanning line drive circuit
17
starts scanning simultaneously from the scanning lines
12
of addresses X
1
and XN+1, and continues to scan sequentially at the same timing from address X
1
to XN, and from address XN+1 to X
2
N.
As shown in
FIG. 50
, the scanning line drive circuit
17
scans the scanning lines
12
sequentially from address X
1
to X
2
N, applies a driving voltage of V(+) or V(−) to a selected scanning line
12
, and applies a operation reference voltage Vref to non-selected scanning lines
12
. The upper signal line drive circuit
15
and lower signal line drive circuit
16
drive the signal lines
10
,
11
at signal line driving voltages VH, VL which are first scanning pulses, depending on the control signal of the control circuit
18
. Output sections of upper signal line drive circuit
15
and lower signal line drive circuit
16
are composed of two analog switches for selecting and issuing one out of two values (VH, VL). The relation of driving voltages V(+), V(−), VH, VL, and Vref should satisfy the following formula (1).
VH−Vref=Vref−VL V=V
(+)−
Vref=Vref−V
(−) (1)
where V is the amplitude of the scanning line driving voltage applied to the liquid crystal cell of each pixel
13
.
The upper signal line drive circuit
15
in
FIG. 49
issues a signal line driving voltage of either VH or VL to M upper signal lines
10
simultaneously in every horizontal scanning, corresponding to the scanning lines from address X
1
to XN. The lower signal line drive circuit
16
issues a signal line driving voltage of either VH or VL to M lower signal lines
11
simultaneously in every horizontal scanning, corresponding to the scanning lines from address XN+1 to X
2
N. The scanning line drive circuit
17
selects the scanning line
12
sequentially in every horizontal scanning, and issues a scanning line driving voltage V(+) or V(−), which is a second scanning pulse, to the selected scanning line
12
from the left side end, and issues an operation reference voltage Vref to the non-selected scanning lines
12
. Therefore, the output section of the scanning line drive circuit
17
is composed of three analog switches for selecting and issuing one out of three values, V(+), V(−), and Vref. The output resistance of these three analog switches (also called ON resistance) is named Ro.
In this way, the liquid crystal panel
14
is driven sequentially. As shown in
FIG. 49
, if the liquid crystal panel
14
is composed of upper and lower screens, the two screens are scanned simultaneously. Accordingly, the output ends of the upper signal line drive circuit
14
and lower signal line drive circuit
15
are provided by the same number.
In such conventional liquid crystal display device of one-end driving of scanning lines, a delay occurs in the driving voltage of each pixel due to presence of wiring resistance r of scanning line
12
and pixel capacitance c. Accordingly, the effective voltage differs slightly in each pixel from the driving end to terminal end of scanning line
12
, and therefore the brightness of each pixel varies slightly from the driving end to terminal end of scanning line
12
. Such luminance unevenness is called a lateral luminance error. Moreover, crosstalk occurs due to distortion of driving voltage of pixels. This is called lateral crosstalk. Similarly, in driving of signal lines, a delay occurs due to wiring resistance of signal line and pixel capacitance, and the brightness of each pixel differs slightly from the driving end to terminal end of signal line, which is a longitudinal luminance error, and crosstalk is caused due to distortion of waveform by signal line driving. It is called longitudinal crosstalk.
Such lateral or longitudinal luminance error or crosstalk become larger as the liquid crystal display device has a wider screen, which was a serious cause of deterioration of picture quality. For development of driving method capable of eliminating the lateral or longitudinal luminance error and crosstalk, drive analysis including the structure of liquid crystal panel an
Kamizono Toshihiko
Kinoshita Hiroshi
Lewis David L.
Matsushita Electric - Industrial Co., Ltd.
Parkhurst & Wendel L.L.P.
Shalwala Bipin
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