Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2007-06-05
2007-06-05
Patel, Nitin I. (Department: 2629)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S092000
Reexamination Certificate
active
10751529
ABSTRACT:
Output signals of two adjacent data signal lines DA1to DAn and DB1to DBn are supplied to comparators CMP1to CMPn, respectively. When pixels are inspected, different signal potentials are input to signal input terminals14aand14b. Signals are written to pixels from the first row to the last row. Thereafter, a pre-charging process is performed by supplying a voltage to the terminals14aand14b. Thereafter, signals are read from all the pixels from the first row to the last row. The signal potentials that have been read are compared by the comparators CMP1to CMPn. Depending on the relations of voltages written as digitally-compared outputs of the comparators CMP1to CMPn, defective pixels are detected.
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Japanese Office Action issued on Jun. 20, 2006.
Ishikawa Kenichiro
Takita Hisashi
Yoshida Joe
Kananen Ronald P.
Patel Nitin I.
Rader & Fishman & Grauer, PLLC
Sony Corporation
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