Computer graphics processing and selective visual display system – Display driving control circuitry
Reexamination Certificate
2000-11-13
2003-11-11
Shankar, Vijay (Department: 2673)
Computer graphics processing and selective visual display system
Display driving control circuitry
C087S026000
Reexamination Certificate
active
06646637
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a liquid crystal display device which incorporates a peripheral circuit and which is designed to receive a digital signal input.
A conventional technique for production of multi-gradation display for a liquid crystal display device is, for example, disclosed in JP-A-5-333817 (1993).
FIGS. 16A through 16D
of the accompanying drawings are views which may be used to illustrate a principle of operation of a D/A conversion circuit which is driven with less reference voltages than the number of gradations to be output, in accordance with the technique disclosed in the above-referenced patent document. With this D/A conversion circuit, five gradation voltages are generated at an output VX from two reference voltages VA and VB.
In the drawings, a switch
91
is a low resistance switch and a switch
92
is a high resistance switch. In the D/A conversion circuit, through control of the switches
91
and
92
as shown in
FIGS. 16A through 16D
, voltages formed by equally dividing the reference voltages VA and VB by four are outputted with respect to the lowest two bits (D
1
, D
0
) of input signal representing gradations to be displayed.
By making use of the circuit arrangement as shown in
FIGS. 16A through 16D
, the D/A conversion circuit can be driven with less reference voltages than the number of gradations to be outputted. Further, by reducing the number of low resistance switches, which require a large area on a semiconductor chip, the area occupied by a driving circuit is reduced, and, thus, the non-display area in the liquid crystal display device can be reduced.
However, with respect to the conventional technique disclosed in the above-referenced patent document, when the D/A conversion circuit is constituted by parallel circuits of high resistance switches and low resistance switches for more than two reference voltages, the output resistance of the D/A conversion circuit varies depending on the input signals representing gradations to be displayed.
Further, at the output portion of the D/A conversion circuit, load capacitances exist, including an OFF capacitance and an ON capacitance, formed by the switches constituting the D/A conversion circuit and the capacitance of a drain line, therefore, these capacitances also need to be driven. Further, these capacitances are independent from the input signals representing gradations to be displayed and are substantially invariable.
When the D/A conversion circuit drives such a capacitance load, a short voltage or a yet attainable margin defined by an attenuation characteristic approximated by a primary order exponential function is induced in the output voltage with respect to a varying input voltage.
FIG. 17
is a graph representing the relationship between short voltage/varying input voltage and conversion time. In
FIG. 17
, the abscissa represents the D/A conversion time and the ordinate represents the short voltage/varying input voltage as a logarithm. The inclination of the attenuation is determined by a product of the load capacitance and the output resistance and varies depending on the output resistance.
FIG. 17
illustrates the difference in attenuation when the output resistance shows the maximum value (R max) and the minimum value (R min), and, as will be observed from the drawing, the two inclinations of attenuation are different. For this reason, although the absolute value of the short voltage decreases in dependance on the lapse of the D/A conversion time, the relative ratios of short voltages/varying input voltages when the output resistances are large and small increase in contrast thereto.
In the above instance, when it is assumed that an allowable short voltage is, for example, about 16 mV for a typical varying input voltage of about 8V, it was necessary in a conventional liquid crystal display device to set a conversion time lower limit Tc and the maximum value Rmax of the switch ON resistance so that the ratio of the short voltage assumes a value below 0.002.
On the other hand, in order to achieve a high resolution, it is necessary to shorten the D/A conversion time as much as possible. However, when there is, for example, a two times difference between the maximum value Rmax and the minimum value Rmin of the output resistance of the D/A conversion circuit, the inclinations of the straight lines become double. In this instance, the ratio of the short voltage 0.002 as it is for the maximum resistance Rmax at the D/A conversion lower limit Tc roughly corresponds to the unevenness or variation of the short voltage, in that it is 16 mV. Since the unevenness in the short voltage appears depending on the gradations, if the D/A conversion time is shortened from the D/A conversion lower limit Tc, this may lead to deterioration of the picture quality because of voltage interval variation between adjacent gradations.
Further, in order to achieve a multi-gradation display, it is required to decrease the unevenness of the short voltage, however, for fulfilling such a requirement, it is necessary to prolong the D/A conversion time.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a liquid crystal display device in which the output resistance of a D/A conversion circuit is kept at a constant value regardless of the gradations to be displayed. With this measure even when the D/A conversion circuit is operated near the D/A conversion time lower limit Tc or with a further slightly shorter conversion time with the result that a short voltage is induced, the voltage interval between the adjacent gradations is hardly varied, because the short voltages between the adjacent gradations are approximated to each other, and a possible deterioration of the picture quality hardly occurs. Thereby, the picture quality is improved and a multi-gradation display can easily be achieved. Further, the conversion time in the D/A conversion circuit can be shortened, and a high resolution can also be achieved.
A liquid crystal display device according to the present invention comprises a pair of substrates at least one of which is transparent, a liquid crystal layer sandwiched between the substrates, a display region and a peripheral circuit for driving the display region, both of which are mounted on one of the pair of substrates. The display region is formed by a plurality of drain lines and a plurality of gate lines arranged in a matrix shape, and a plurality of thin film transistors are each disposed near the respective cross points of the matrix. The peripheral circuit is provided with a driving circuit which is signed to receive digital image signal inputs. The driving circuit is provided with a plurality of D/A conversion circuits, each being constituted by a plurality of switches, each having substantially the same ON resistance, and a control unit which controls ON and OFF operation of the switches in such a manner that, at the time of a D/A conversion operation, a plurality of switches in a corresponding number are turned ON for respective input signals representing respective gradations.
In the above-described liquid crystal display device, the D/A conversion circuit can be constituted by a plurality of switch groups, each being constituted by a plurality of switches connected in parallel. One of the terminals of each of the respective switch groups is respectively connected to different wiring lines for supplying respectively different reference voltages, the other terminals of the switch groups are connected in common to constitute a voltage output portion, and the control unit operates to turn ON a predetermined number n of switches among one or two of the switch groups.
Further, it is preferable to maintain the following relationship with respect to a range of unevenness of the ON resistance of the switches;
r/R
<2
wherein, R represents a center value of ON resistances of the switches, r represents the difference between the maximum value and the minimum value of the ON resistances of the switches and n represents the number of switches bei
Kageyama Hiroshi
Mikami Yoshiro
Sato Hideo
Antonelli Terry Stout & Kraus LLP
Said Mansour M.
Shankar Vijay
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