Liquid crystal cells – elements and systems – Particular structure – Interconnection of plural cells in parallel
Reexamination Certificate
2000-07-06
2003-06-03
Sikes, William L. (Department: 2871)
Liquid crystal cells, elements and systems
Particular structure
Interconnection of plural cells in parallel
C349S044000, C349S153000, C349S110000
Reexamination Certificate
active
06573957
ABSTRACT:
BACKGROUND OF THE INVENTION
Technical Field
The present invention relates to a liquid crystal display (LCD) device. More particularly, the present invention relates to the LCD device including a tiling panel in which a plurality of discrete LCD panels are bonded together to form a large size display screen.
PRIOR ART
The LCD device using as the tiling panel has been developed, in which a plurality of discrete LCD panels are bonded together.
FIG. 1
shows the LCD device using the tiling panel to which the technology of the present invention is applicable. In the
FIG. 1
, the tiling panel includes four discrete LCD panels A, B, C and D, for example, which are bonded together along a bonding region
19
. A cross point of the vertical bonding region
19
and the horizontal bonding region
19
is a center point (CT) of the tiling panel. Each of the LCD panels A, B, C and D includes a lower glass substrate
1
and an upper glass substrate
2
. Next, the positional relationship of the pixels of the LCD panels A, B, C and D, which are located adjacent to the bonding region
19
, is described.
FIG. 2
shows an arrangement of pixel regions of the LCD panels A, B, C and D. It is assumed that a width of a black matrix disposed between the adjacent two pixel region in the horizontal direction is LH, and a width of the black matrix disposed between the adjacent two pixel regions in the vertical direction is LV. To display the natural and continuous image across the bonding regions
19
, the distance between the pixel region PMN at the most lower right position of the panel A and the pixel region PM
1
at the most lower left position of the panel B, and the distance between the pixel region P
1
N at the most upper, right position of the panel D and the pixel region P
11
at the most upper left position of the panel C should be the distance represented by 2L
1
+LB, wherein the L
1
<LH/2, and LB is the width of the bonding region
19
. Further, the distance between the pixel region PMN of the panel A and the pixel region P
1
N of the panel D, and the distance between the pixel region PM
1
of the panel B and the pixel region P
11
of the panel C should be the distance represented by 2L
2
+LB, wherein the L
2
<LV/2. A sealing regions
8
, later described, are shown by the dashed line in the FIG.
2
.
Describing a structure of one LCD panel, such as the LCD panel A, used for the tiling panel, with reference to FIG.
3
. The
FIG. 3
shows the structure on the lower glass substrate
1
and the upper glass substrate
2
of the panel A. On the surface of the lower glass substrate
1
, a plurality of data lines DL
1
through DLN are formed along the vertical direction, a plurality of gate lines GL
1
through GLM are formed along the horizontal direction, one pixel region including a thin film transistor (TFT)
3
and the pixel electrode
4
defining one pixel (P) is formed at each of the cross points of the data lines and the gate lines, an outer short ring
5
and an inner short ring
6
made of an electrically conductive material are formed, and an alignment layer made of polyimide, not shown in the
FIGS. 1 and 2
are formed. The arrangement of the liquid crystal molecules is decided by a rubbing direction on the surface of the alignment layer, in the rubbing process. On the surface of the upper glass substrate
2
, a common electrode and the alignment layer, not shown in the
FIGS. 1 and 2
, are formed. In the case of a color LCD device, color filters, i.e. Red color filters, Green color filters and Blue color filters, are formed on the upper glass substrate
2
.
At the completion of the lower glass substrate
1
, both the outer and inner short rings
5
and
6
are formed. The lower glass substrate
1
is cut along cutting lines
9
A through
9
D, so that the outer short ring
5
and the right side portion and the lower portion of the inner short ring
6
are removed. Before the cutting process, the outer short ring
5
is connected to a potential level corresponding to the potential level of the common electrode. The outer short ring
5
is connected to the inner short ring
6
through resistive element
7
. Each of the data lines DL
1
through DLN is connected to the outer short ring
5
and the inner short ring
6
through the resistive element
7
, respectively, and each of the gate lines GL
1
through GLM is connected to the outer short ring
5
and the inner short ring
6
through the resistive element
7
, respectively. The purpose of the outer and inner short rings
5
and
6
is to prevent the TFT
3
of the pixel region from being damaged by electrostatic discharge (ESD) during the fabrication of the LCD panel, in the following manner. A resistive value of the resistive element
7
, such as a TFT operating as a diode, is designed to be lower than a resistive value of the TFT
3
of the pixel region. When the electrostatic charges are applied to the gate lines, for example, during the handling of the lower glass substrate
1
, the resistive element
7
connected between the gate lines and the short ring
6
, and the resistive element
7
connected between the short ring
8
and the data lines conduct, whereby the electric potential level at the gate lines becomes equal to the electric potential at the data lines, and no voltage is applied between the drain and gate electrodes of the TFT
3
of the pixel region. After the cutting of the lower glass substrate
1
and the assemble of the upper glass substrate
2
on the lower glass substrate
1
, the inner short ring
6
is connected to the common electrode on the upper glass substrate
2
, so that when the electrostatic charges are applied to the gate line(s) or the data line(s), the resistive elements
7
conduct to pass the electrostatic charges to the common electrode through the inner ring
6
, resulting that the electric potential level at the lower glass substrate
1
becomes equal to the electric potential of the common electrode on at the upper glass substrate
2
, and no voltage is applied to the TFT
3
of the pixel region.
The lower glass substrate
1
and the upper glass substrate
2
are sealed along the sealing region
8
to complete the panel A, as well known in the art. Describing the formation of the sealing region
8
of the panel A with reference to the
FIG. 2
, the right side portion of the sealing region
8
is formed adjacent to the pixel regions of the right most data line DLN, and the lower side portion of the sealing region
8
is formed adjacent to the pixel regions of the lower most gate line GLM, to provide the distance L
1
and the distance L
2
(FIG.
2
), respectively after the cutting process. It is required to provide the positional relationship of the pixel regions on the LCD panels A, B, C and D, as shown in the FIG.
2
. For this reason, the right side and lower side portions of the sealing region
8
are formed inside of the inner short ring
6
. A typical width W
1
of the sealing region
8
is about 500 through 1000 &mgr;m, and the width W
2
of the sealing area
8
remaining along the cutting lines
9
B and
9
D is about 50 through 100 &mgr;m. Therefore, the LCD panel A includes the short ring
6
along the upper side and the left side, and does not include the short ring
6
along the right side and the lower side. A flexible circuit board or TAB (Tape Automated Bonding) tape, on which circuit modules, such as data line drivers are mounted, is connected to the data lines, which are exposed in an upper side area
10
(FIG.
3
), and a flexible circuit board or the TAB tape, on which circuit modules, such as gate line drivers are mounted, is connected to the gate lines, which are exposed on a left side area
11
(FIG.
3
). In a similar manner as the LCD panel A, the LCD panels B, C and D are formed by changing the position of the cutting lines.
The four LCD panels A, B, C and D constitutes one LCD display screen, and the data line drivers of the four LCD panels and the gate line drivers of the four LCD panels are controlled to display the image on the four LCD panels.
To bond t
Akkapeddi P. R.
Scully Scott Murphy & Presser
Sikes William L.
Underweiser, Esq. Marian
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