Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-03-22
2002-12-17
Shankar, Vijay (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S098000, C345S099000, C345S100000
Reexamination Certificate
active
06496169
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a liquid crystal display device having the structure in which a liquid crystal display device of an active matrix type and a timing control circuit are formed of thin film transistors having the structures identical to each other, which are formed on the same substrate.
In general, liquid crystal display apparatus have the characteristics of light weight, thin in measurements, a low-consumption power, and the like, as compared to other display devices such as cathode ray tube and the like. For this reason, the liquid crystal display apparatus are widely used as the display device for a television set, a mobile data terminal, a graphic display or the like.
An example of the liquid crystal display apparatus is an active matrix type liquid crystal display apparatus having a structure in which thin film transistors (to be called TFT(s) hereinafter) which operate as switching elements are arranged. The active matrix-type liquid crystal display apparatus has a high-speed responsibility, and is capable of increasing the clearness and fineness of a displayed image, and therefore the display apparatus of this type is becoming more popular as an element for achieving the current demands, that is, a higher quality of the display screen, an increase in the size of the screen, and a color image.
Further, recently, there are demands of narrowing the frame of the screen decreasing the thickness of the apparatus, and increasing the clearness and fineness of a screen. In order to meet such demands, a drive-circuit-monolithic type liquid crystal display apparatus equipped with a built-in drive circuit has been proposed.
The drive-circuit-monolithic type liquid crystal display apparatus has a characteristic structure in which a signal line drive circuit and a scan line drive circuit are arranged on the same substrate.
FIG. 5
is a diagram showing an example of the conventional circuit structure of a signal line drive circuit, and
FIG. 6
is a diagram showing an example of the drive waveforms of the circuit.
This signal line drive circuit consists of a plurality of shift registers
1
a,
1
b,
. . . ,
1
n
, a plurality of buffer circuits
2
a,
2
b,
. . .
2
n,
a plurality of analog switch groups
3
a,
2
b, . . .
3
n,
and a plurality of video bus lines
4
a,
4
b,
. . .
4
n.
With the above structure, input video signal on a video bus line
4
is transferred to a signal line
6
in a display region
5
via an analog switch
3
.
The switching operation of the switches is controlled by a shift register circuit
1
.
A number of the neighboring switches
3
are connected with a single shift register to be switched at the same time. As a result, the signal lines
6
connected to the neighboring switches
3
are charged at the same time. Such neighboring switches and signal lines are called a “circuit block” hereafter.
To the shift register circuit
1
, a start pulse XST, and two kinds of clock signals XCK and/XCK having different phases from each other are input. A timing chart at these signals is shown in FIG.
6
. The start pulse XST is latched by the shift register and output therefrom as shift data, in synchronism with the clock signals.
In the above-described drive-circuit-integrated type liquid crystal display apparatus, drive-circuits are composed of TFTs witch are formed on a glass substrate, and therefore the characteristics is unstable as compared to a single-crystalline silicon semiconductor circuit.
Due to the unstable characteristics, the time delay or the distortion of the control signals would occur. As a result, the control signals of adjacent analog switches are overlapped each other and so called “ghost” phenomena is observed.
Next, above a ghost phenomena will now be described in more detail.
FIG. 7
shows a normal operation of analog switches. In this case, adjacent pulses have no overlapping portion with each other.
FIG. 8
shows the case that adjacent pulses partially overlap with each other. The waveform b shows an input video signal voltage applied on a video bus line at predetermined period, a waveform c shows an input voltage for the next block applied at one previous horizontal period, and a waveform d shows actual voltage of the video bus line at the predetermined period.
If the adjacent pulses are partially overlapped, a voltage charged in a signal line c of the next block leaks into a video bus line of the block to which a signal is currently input, via an analog switch, as the analog switch is opened.
As a result, the video signal on the bus line is affected by the voltage stored in the signal line capacitance of the next block, to have a voltage waveform
92
, and a voltage with the above-described waveform is charged to the signal line; therefore the ghost of one previous horizontal period appears on the screen.
Technical measures for preventing the occurrence of a ghost, are discussed in, for example, Jpn. Pat. Appln. KOKAI Publication No. 5-216441, which proposes a horizontal scanning circuit which can cut a top end portion of a shift pulse until the fall timing of a one previous shift pulse, so as to avoid a superimposing section.
FIG. 9
shows a schematic structure of the technique of the KOKAI publication, and
FIG. 10
shows signal waveforms obtained with the technique shown in FIG.
9
.
The structure shown here has an arrangement in which a two-terminal input type NOR circuit serving as a fixed pattering removing circuit is added to an output signal terminal side of each of shift registers S/R.
In the circuit structure, a shift pulse (shift register output signal) Dn+1 output from the shift register is inverted by NANDn+1 into a primary pulse signal Bn+1.
The primary pulse signal Bn+1 is input to one of the input terminals of NORn+1 situated on the line, and a pulse signal &PHgr;n for driving a switching transistor S, which is output from a delay circuit DLYn of a previous stage is split and input to the other input terminal.
Then, a secondary pulse signal Cn+1 which is a negative logic sum (negative OR) of the primary pulse signal Bn+1 and the pulse signal &PHgr;n is output from NORn+1. The secondary pulse signal Cn+1 is delayed by a predetermined time t by the delay circuit DYLn+1, and thus a pulse signal &PHgr;n+1 is output.
In other words, the portion A of the primary pulse signal Bn+1, which is the superimposing section of the shift register output signal, is cut out up to the fall of the secondary pulse signal of one previous stage, and further delayed by a predetermined time t by the delay circuit DLY.
Therefore, as can be seen in
FIG. 10
, the superimposing section A between a pulse signal (analog switch control signal) &PHgr;n for driving a switching transistor Sn and a switch transistor Sn+1, and a pulse signal &PHgr;n+1, is removed, and further delayed by a predetermined time t. In this manner, ideally, the occurrence of a ghost should be suppressed.
In reality, however, a shift pulse Dn serving as a shift register output signal, that is, analog switch control signal takes a form shown in
FIG. 11
as compared to an input start pulse XST.
The shift pulse Dn (solid line) is output in the waveform obtained by differentiating a start pulse XST having a square waveform by means of the internal delay of a flip-flop circuit included in the register shown in FIG.
9
.
The rise characteristics of a shift pulse Dn is dependent mainly on the voltage-current characteristics of p-ch TFT which constitutes a clocked inverter within the flip-flop circuit, whereas the breaking characteristics thereof is dependent the voltage-current characteristics of n-ch TFT.
In general, the carrier mobility in a n-ch TFT is higher than that in a p-ch TFT, and therefore the absolute amount of the unevenness of the characteristics is larger in the case of an n-ch TFT. Further, in the case where a so-called LDD (lightly doped drain) structure is employed in an n-ch TFT, the manufacturing process therefor becomes more complex than the case of a
Kabushiki Kaisha Toshiba
Pillsbury & Winthrop LLP
Shankar Vijay
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