Liquid crystal display device

Liquid crystal cells – elements and systems – Particular excitation of liquid crystal – Electrical excitation of liquid crystal

Reexamination Certificate

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Details

C349S043000

Reexamination Certificate

active

06445427

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display having an improved display area.
2. Description of the Related Art
In general, an active matrix type-liquid crystal display; AM-LCD) device is thin, so that it is often used in various display devices. In this AM-LCD device, one thin film transistor(TFT) is provided as a switching element for each pixel, so that individual pixel electrodes are independently driven. The contrast is therefore not reduced based upon the reduction of a duty ratio, and also the angle of visibility is not reduced, even when the capacity of display is increased to increase the number of lines.
FIG. 1
shows a plane view of an array substrate in the conventional AM-LCD.
Referring to
FIG. 1
, a gate line
21
and a data line
22
are arranged in the shape of matrix on a cell region
20
of an array substrate
10
. ESD(ElectroStatic Discharge) protection parts
31
and
32
are disposed on an outside substrate
10
of the cell region
20
, respectively. The ESD protection parts
31
and
32
are connected to input portions of the gate line
21
and the data line
22
, respectively, thereby protecting the gate line
21
and the data line
22
from ESD.
However, since the area of the cell region
20
is limited due to the ESD protection parts
31
and
32
, it is limited to improve display area.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a liquid crystal display device which can protect a cell region from ESD and improve a display area, for solving the problems in the conventional art.
To accomplish this above object, a liquid crystal display device according to the present invention, includes: a cell region arranged on the overall region of an array substrate; a gate line and a data line arranged in the shape of matrix on the cell region; an ESD protection part disposed at one side of a cross portion of the gate line and the data line, the ESD protection part protecting the gate line and the data line from ESD; and a thin film transistor disposed at the other side of the cross portion, the thin film transistor acting as a switching element.
Furthermore, in the ESD protection part, one side of the gate line is in contact with a source/drain metal pad, one side of the data line is in contact with a gate metal pad, and the other side of the gate line is in contact with a source/drain metal layer. Preferably, the distance between the ESD protection part and the thin film transistor is ¼ to ⅓ of a pitch size.
Moreover, the ESD protection part includes first and second transistors and both the first and second transistors are a NMOS transistor. Here, a gate of the first transistor is connected to a source thereof, a drain of the first transistor is connected to a gate of the second transistor, and the gate of the second transistor is connected to a source thereof.
Additional object, advantages and novel features of the invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.


REFERENCES:
patent: 5671026 (1997-09-01), Shiraki et al.
patent: 5909035 (1999-06-01), Kim
patent: 6043971 (2000-03-01), Song et al.
patent: 6081307 (2000-06-01), Ha
patent: 60203919 (1985-10-01), None

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